Intel Corporation

Melik Isbara

David Wyatt

John B Halbert

Jun Shi

Animesh Mishra

Sandeep K Jain

The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Temperature determination and communication for multiple devices of a memory module

Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

A buffer circuit is used to convert signals of a first preselected voltage level to a second preselected voltage level. A pass gate transistor has a gate, source, and drain and is adapted to receive the signals of the first preselected voltage level, and deliver the signals of the second preselected voltage level. A capacitor is coupled across the source and drain of the pass gate transistor. A resistive element is coupled between the gate of the pass gate transistor and a voltage supply. The resistive element cooperates with a parasitic capacitance located between the gate and source of the pass gate transistor to form a pump that reacts to a low-to-high transition in the input signal to temporarily increase the voltage level applied to the gate of the pass gate transistor. This temporarily increased voltage level causes the voltage level output from the pass gate transition to track the transition in the input signal more closely.

Method and apparatus for interfacing mixed voltage signals

A high voltage drive output buffer for low voltage integrated circuits comprising a pullup pFET; a driver pFET having a source connected to the drain of the pullup pFET, and having a gate connected to a biasing circuit; a driver nFET having a drain connected to the drain of the driver pFET, and having a gate connected so as to be biased; and a pulldown nFET having a drain connected to the source of the driver nFET; wherein the pullup pFET and pulldown nFET are coupled to switch in complementary fashion in response to an input voltage; and wherein the biasing circuit comprises an nFET having a drain connected to the gate of the driver pFET and coupled to the input node so as to switch ON for a transitory period when the pullup pFET switches from OFF to ON.

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Hillsboro, OR, United States of America

Melik Isbara