Hrl Laboratories, LLC

Gm Global Technolgoy Operations, Inc.

Northrop Grumman Systems Corporation

Melanie Sachiko Yajima

Florian G Herrault

Alexandros Margomenos

Miroslav Micovic

Igal Bilik

Hyok Jae Song

Hasan Sharifi

Wonill Ha

Keerti S Kona

Eric M Prophet

Xianglin Zeng

Patty Pei-Ling Chang-Chien

Matthew Borselli

Sieu Ha

Maggy Lau

Christopher Bohn

Maxwell Choi

Clayton Jackson

Chi Kong Cheung

One or more embodiments of the present disclosure are directed toward improved methods of fabricating a semiconductor device utilizing multi-level electron beam lithography (e-beam lithography), an alignment marker for multi-level e-beam lithography, and a semiconductor device including the alignment marker. A method of fabricating a semiconductor device may include: forming an alignment marker in a substrate, the alignment marker including tantalum; determining, utilizing a backscatter electron detector of an electron beam lithography tool, a location of an edge of the alignment marker based on an atomic number contrast between the alignment marker and the substrate; and forming, utilizing the electron beam lithography tool, at least one transistor in the substrate based on the location of the edge of the alignment marker.

Embedded high-Z marker material and process for alignment of multilevel ebeam lithography

A microfabricated laminated conductor, comprising at least two flat metallic conductors held together parallel by their edges by a first dielectric material anchor, such that there exists a gap of between several nanometers and several micrometers between most of the at least two flat metallic conductors.

Laminated conductors

The present application generally relates communications and hazard avoidance within a monitored driving environment. More specifically, the application teaches a system for semi-transparent and flexible millimeter wave circuits and antennas using inexpensive PET substrate. The system facilitates the fabrication of millimeter wave circuits, transmission lines and antennas in various optically transparent platform where optical transparency is desired, for example in automotive radar in windows, windshield, and rear/side mirrors.

Method and apparatus for semitransparent antenna and transmission lines

A method for fabricating high-resolution features in a deep recess includes etching a cavity in a substrate, fabricating at least one focusing pattern on a bottom of the cavity, wherein fabricating the focusing pattern comprises coating a first photoresist on the bottom of the cavity, patterning the first photoresist to define a focusing etch area using contact lithography, and etching the focusing etch area, coating a second photoresist on the bottom of the cavity, using the focusing pattern to focus a high resolution lithography tool at the bottom of the cavity to pattern the second photoresist to define a microfabrication feature area; and forming a microfabrication feature in the microfabrication feature area.

Formation of high-resolution patterns inside deep cavities and applications to RF Si-embedded inductors

An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Wafer-level die to package and die to die interconnects suspended over integrated heat sinks

Formation of high-resolution patterns inside deep cavities and applications to RF SI-embedded inductors

A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.

Direct IC-to-package wafer level packaging with integrated thermal heat spreaders

A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.

Method of integration of wafer level heat spreaders and backside interconnects on microelectronics  wafers

A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.

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Los Angeles, CA, United States of America

Melanie Sachiko Yajima