International Business Machines Corporation

Freescale Semiconductor,inc.

Chartered Semiconductor Manufacturing Ltd (corporation)

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Infineon Technologies North America Corp.

Globalfoundries U.S. 2 LLC

Melanie J Sherony

Terence B Hook

Xiangdong Chen

Dae-Gyu Park

Christopher M Schnabel

Weipeng Li

Steven H Voldman

James A Culp

Werner A Rausch

Kenneth Jay Stein

Jin-Ping Han

Yong Meng Lee

Da Zhang

Laegu Kang

Jawahar P Nayak

Noah D Zamdmer

Chendong Zhu

Vijay Narayanan

Haizhou Yin

Dominic Joseph Schepis

Voon-Yew Thean

Anda C Mocuta

Young Way Teh

Scott W Crowder

Christopher V Baiocco

Helen Wang

Jay M Shah

Young Gun Ko

Franck Arnaud

Embodiments of the present invention disclose a semiconductor structure and method for establishing a thermal profile across a semiconductor chip. In certain embodiments, the semiconductor structure comprises a through-silicon via formed in a first semiconductor chip having thermal control circuitry, wherein the through-silicon via is formed in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, and wherein the through-silicon via conducts heat from the thermal control circuitry to the region. In other embodiments, the method comprises forming a through-silicon via in a first semiconductor chip having thermal control circuitry. The method also comprises forming the through-silicon via in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, wherein the through-silicon via conducts heat from the thermal control circuitry to the region.

Establishing a thermal profile across a semiconductor chip

Methods for packaging a functional chip, methods for annealing a functional chip, and chip assemblies. A functional chip and an annealing chip are located inside a package. The functional chip includes an integrated circuit. The annealing chip includes an annealing element source comprised of an annealing element or a light source configured to emit electromagnetic radiation. The integrated circuit of the functional chip receives the annealing element, electromagnetic radiation, or both from the annealing chip in order to perform an annealing procedure that extends the useful lifetime of the packaged integrated circuit.

In-situ annealing for extending the lifetime of CMOS products

Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.

In-situ relaxation for improved CMOS product lifetime

A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.

Self-limiting oxygen seal for high-K dielectric and design structure

An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

High pressure deuterium treatment for semiconductor/high-K insulator interface

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Threshold voltage improvement employing fluorine implantation and adjustment oxide layer

A semiconductor process and apparatus fabricate a metal gate electrode () and an integrated semiconductor resistor () by forming a metal-based layer () and semiconductor layer () over a gate dielectric layer () and then selectively implanting the resistor semiconductor layer () in a resistor area () to create a conductive upper region () and a conduction barrier (), thereby confining current flow in the resistor semiconductor layer () to only the top region () in the finally formed device.

Semiconductor resistor formed in metal gate stack

An integrated circuit (IC) is provided that includes at least one static random access memory (SRAM) cell wherein performance of the SRAM cell is enhanced, yet with good stability and writability. In particular, the present invention provides an IC including at least one SRAM cell wherein the gamma ratio is about 1 or greater. The gamma ratio is increased with degraded pFET device performance. Morever, in the inventive IC there is no stress liner boundary present in the SRAM region and ion variation for all devices is reduced as compared to that of a conventional SRAM structure. The present invention provides an integrated circuit (IC) that comprises at least one SRAM cell including at least one nFET and at least one pFET; and a continuous relaxed stressed liner located above and adjoining the nFET and the pFET.

Structure of static random access memory with stress engineering for stability

A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Halo-free non-rectifying contact on chip with halo source/drain diffusion

A semiconductor device having a silicon-on-insulator (SOI) structure includes a field-effect transistor having amorphized source and drain regions formed by implanting silicon or germanium ions into a silicon layer formed over a buried insulator. The fully amorphized source and drain regions ultimately result in permanent crystalline defects that cause p-n junction leakage which allows charge in the body of the device to dissipate, thereby improving the overall efficiency and performance of the device. The source and drain regions are amorphized throughout their entire thickness to prevent single crystal re-crystallization from occurring during annealing and other subsequent processing steps that can degrade the quality of the p-n leakage junctions.

Fully amorphized source/drain for leaky junctions

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Fishkill, NY, United States of America

Melanie J Sherony