Arm Limited

Melanie Emanuelle Lucie Teyssier

Florent Begon

Jocelyn Francois Orion Jaubert

Frederic Claude Marie Piry

Luca Scalabrino

Guillaume Schon

Nicolas Jean Phillippe Huot

Simon John Craske

Nicolas Chaussade

Philippe Jean-Pierre Raphalen

Gilles Eric Grandou

Albin Pierick Tonnerre

A data processing system () includes memory protection circuitry () storing access control data for controlling accesses to data at memory addresses within a main memory (). An access control cache () may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry () to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache () is storing access control data for a memory access request, then the access control data stored within the access control cache () is used in place of access control data retrieved form the memory protection circuitry (). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

Provision of access control data within a data processing system

A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency. If the execution circuitry does not complete execution of that instance of the predetermined type of instruction due to occurrence of a predetermined event, the data processing apparatus is arranged to reinstate the state of the data processing apparatus with reference to the checkpoint information, such that the execution circuitry is then configured to recommence execution of the sequence of program instructions at that instance of the predetermined type of instruction.

Marking long latency instruction as branch in pending instruction table and handle as mis-predicted branch upon interrupting event to return to checkpointed state

First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Tracking speculative execution of instructions for a register renaming data store

A data processing apparatus is provided in which a processor unit accesses data values stored in a memory and a cache stores local copies of a subset of the data values. The cache maintains a status value for each local copy stored in the cache. When the processor unit executes a load-exclusive operation, a first data value is loaded from a specified memory location and an exclusive use monitor begins monitoring the specified memory location for accesses. When the processor unit executes a store-exclusive operation, a second data value is stored to the specified memory location if the exclusive use monitor indicates that the first data value has not been modified since the load-exclusive operation was executed. When a local copy of the first data value is stored in the cache and the status value for the local copy of the first data value indicates that the processor unit has exclusive usage of the first data value, the data processing apparatus is configured to prevent modification of the status value for a predetermined time period after the processor unit has executed the load-exclusive operation.

Data processing apparatus and method for performing load-exclusive and store-exclusive operations

A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.

Apparatus and method for predicting target storage unit

A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an age-ordered list of entries corresponding to instructions issued to the processing pipeline for execution. The unit is configured to store, in association with each entry, an exception indicator indicating whether the instruction is an exception instruction and whether it has generated an exception and an error indicator indicating whether the instruction has generated an error. The apparatus is configured to indicate to the exception storage unit that an instruction is resolved when processing of the instruction has reached a stage such that it is known whether the instruction will generate an error and whether the instruction will generate an exception; and the exception control circuitry is configured to sequentially retire oldest resolved entries from the list in the exception storage unit.

Recovering from exceptions and timing errors

A data processing systemis provided with multiple processor coreseach incorporating a data cache memory. A snoop control unitmanages coherency between the data values stored within the data caches. The snoop control unitincorporates a TAG memory. If an error is detected within an entry of the TAG memory, then a hit operation is forced to the corresponding storage location one or more of the data caches

Growing community of inventors

Grasse, France

Melanie Emanuelle Lucie Teyssier