Advanced Micro Devices Corporation

Melanie D Typaldos

John Phillip Hansen

Bruce A Loyer

Patrick Evan Maupin

David A Spilo

Ronald W Stence

Eric G Chambers

Wade L Williams

Louis R Stott

Martin Schuessler

Hock-Koon Lee

A microcontroller employs an asynchronous serial port for predictably updating a baud divisor during data reception. A write enable to the baud counter ensures that the current value of the baud count in the baud counter is greater than a predetermined number of clocks so that the working baud divisor to be loaded from the working baud divisor register is stabilized. The working baud divisor register is updated during data reception by the serial port by a software write to a visible baud divisor register provided the working baud divisor in the working baud divisor register is not being used to load the baud counter. A working baud divisor register thereby maintains a value guaranteed to be stable by the time a baud counter needs to be reloaded. A visible baud divisor register and the baud counter can be on different, possibly asynchronous clocks.

Predictable updating of a baud divisor of an asynchronous serial port during data reception

A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the &ldquo;compressive&rdquo; DMA.

Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers

An asynchronous receiver/transmitter provides autobauding with adjustment to a programmable baud rate. A baud divisor is calculated based on a detected size of a start bit. The asynchronous receiver/transmitter provides a plurality of baud divisor replacement registers, each register storing a baud divisor threshold and a baud divisor replacement. The baud divisor is compared to the plurality of programmed baud divisor thresholds. Based on the performed hardware comparison, the baud divisor is automatically replaced by a baud divisor replacement for a particular baud divisor range defined by a baud divisor threshold and including the baud divisor. The baud rate corresponding to this baud divisor replacement represents the appropriate baud rate. Autobauding with adjustment to a programmed baud rate corrects for measurement inaccuracies with respect to the start bit size. Autobauding with adjustment to a programmed baud rate also permits an asynchronous receiver/transmitter to reliably support high speed baud rates. Further, the programmable nature of the baud divisor thresholds and baud divisor replacements permits an asynchronous receiver/transmitter to support autubauding at multiple asynchronous receiver/transmitter frequencies.

Autobauding with adjustment to a programmable baud rate

An asynchronous serial port provides automatic parity generation and detection in frames supporting address bits. In data frames comprising a variable number of data bits, the parity bit is located immediately following the last data bit and before the address bit. Parity generation is performed automatically based only on the preceding data bits. Parity detection allows interrupts to be generated directly from the parity bit received. Further, parity generation and detection is not dependent on the number of bits in the data frame.

UART automatic parity support for frames with address bits

An asynchronous serial port provides increased serial throughput. In data frames comprising eight data bits, at least one bit may be disabled. The status and communication bits within the frame are moved into the locations of the disabled bits. The number of bits in the transmission data frame is thus reduced by the number of disabled data bits.

UART support for address bit on seven bit frames

A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.

Test mode programmable reset for a watchdog timer

A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.

Emulator support mode for disabling and reconfiguring timeouts of a

An asynchronous serial port is provided in a microcontroller that includes an address matching function that includes character matching functions such that incoming data is compared to match registers for special framing characters. Further, however, address bits are provided within the serial data, and additional matching bits are provided for matching those address bits along with the character data within the matching registers. In this way, not only is framing data detected by the detection of special characters, but a microcontroller can determine when it is being addressed in a multidrop, address bit protocol system by matching the address bit and address data.

UART character matching used for address matching on a

A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., execution unit) when a data frame having a last data bit equal to a predetermined value is received. Such hardware features allow the execution unit to determine when complete data packets are received. Each ASP is adapted to receive serial communication data, and is configurable to generate an internal DMA request signal in response to the serial communication data. The serial communication data is transmitted within data frames, wherein each data frame includes multiple data bits transmitted sequentially between a start bit and one or more stop bits. The last data bit of the multiple data bits is transmitted immediately before the one or more stop bits. Each ASP is configurable to generate an ASP interrupt request signal when the value of the last of the multiple data bits is equal to a predetermined value, preferably when the last data bit is set to 1 as commonly used to signal the beginning or end of a data packet. Each ASP includes at least one configuration register, the contents of which determine the operation of the ASP. Generation of the ASP interrupt request signal and the internal DMA request signal is determined by the contents of at least one bit position within the configuration register.

System for performing DMA transfers where an interrupt request signal is

An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.

System having a receive data register for storing at least nine data

A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA). The microcontroller includes an execution unit, a DMA unit, one or more ASPs, and at least one input/output (I/O) pad formed upon a single monolithic semiconductor substrate. The execution unit is configured to execute instructions, preferably .times.86 instructions. Each ASP is configurable to generate an internal DMA request signal, which effectuates a DMA transfer of serial communication data, and multiple DMA control signals. Each I/O pad is adapted to receive an external DMA request signal generated by a device external to the microcontroller. The DMA unit includes selection logic coupled to one or more DMA channel circuits. The selection logic receives the internal and external DMA request signals as well as the DMA control signals, and produces a DMA request signal for each DMA channel circuit. Each DMA request signal is either an internal DMA request signal or an external DMA request signal, depending upon the DMA control signals. Each DMA channel circuit receives the corresponding DMA request signal and performs a data transfer operation in response to the DMA request signal. During the DMA transfer operation, data is read from a first address and written to a second address. Each ASP and DMA channel circuit includes at least one configuration register, the contents of which determine the operation of the ASP or DMA channel circuit.

System for selecting between internal and external DMA request where ASP

A microcontroller integrates an internal memory accessible by the cores included thereon. Logic within the microcontroller compares memory addresses generated by the cores to values in a configuration register specifying a memory address range in which the internal memory resides. The logic generates a chip select signal to the internal memory if the memory address generated resides within the specified address range to enable accesses by the cores to the internal memory. The integrated circuit may be configured in a debug mode wherein the chip select signal is inhibited to the internal memory, however the chip select signal is provided external to the integrated circuit on a pin. The chip select signal may then be used to select an external memory which serves to overlay the internal memory address range. Thus the debug mode allows instruction code and data to reside in the external memory rather than the internal memory while in the debug mode. This facilitates debugging of the code since the contents of the external memory may be examined, for example by an in-circuit emulator, in a less intrusive manner than the contents of the internal memory may be examined. The debug mode may be enabled by asserting a signal upon a predefined pin at the conclusion of reset of the microcontroller. By providing the predefined pin for placing the microcontroller into the debug mode, the microcontroller may be placed into the debug mode for debug purposes without changing the instruction code being executed thereon. Furthermore, the in-circuit emulator need not have knowledge of the internal memory address range.

Growing community of inventors

Buda, TX, United States of America

Melanie D Typaldos