Intel Corporation

Melaku Teshome

Josh B Mastronarde

Altug Koker

Varghese George

Sanjeev S Jahagirdar

Lakshminarayanan Striramassarma

Iqbal Rajwani

Vikranth Vemulapalli

Naveen Matam

Lance Cheney

Eric Finley

Binoj Xavier

William S Dubel

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUs based on chiplet configurations

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of system-on-chip (SOC) architecture

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of System-On-Chip (SOC) architecture

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUS based on chiplet configurations

Disaggregation of SOC architecture

Embodiments are generally directed to automatic waking of power domains for graphics configuration requests. An embodiment of an apparatus an interface to receive a graphics configuration request, wherein the graphics configuration request is directed to a target graphics register in a graphics domain; registers for storage of data, the registers including one or more configuration registers that are accessible for storage of the graphics configuration request; automatic power domain determination logic to determine a power domain for the target graphics register based on shared information accessed by the automatic power domain determination logic; and wake indication logic to determine whether the power domain for the target graphics register is in a reduced power state and, upon making a reduced power state determination, to generate a wake indication for the power domain.

Automatic waking of power domains for graphics configuration requests

Growing community of inventors

El Dorado Hills, CA, United States of America

Melaku Teshome