Intel Corporation

Marvell Israel (misl) Ltd.

Mel Bazes

Rafi Ben-Tal

In a circuit having a runaway detector coupled to a phase-locked loop (PLL), the PLL may include a loop filter to receive a control voltage within the PLL and provide a filtered control voltage and a voltage-controlled oscillator to receive the filtered control voltage and provide an output clock signal. The runaway detector may provide a control signal for adjusting the filtered control voltage in response to a predetermined PLL condition. The runaway detector may include a comparator to receive a first and second input voltages, where the second input voltage is based on the output clock signal. When the predetermined PLL condition exists, the runaway detector may be active to adjust the filtered control voltage, thereby enabling the PLL to return to a lock condition.

Phase-locked loop runaway detector

Some of the embodiments of the present disclosure provide a D-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed.

Race free semi-dynamic D-type flip flop

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a signal generation circuit. The signal generation circuit is configured to generate a first output signal and a second output signal in response to a reference signal. The first output signal and the second output signal are a pair of complementary signals. The first output signal has first transitions of a first polarity and second transitions of a second polarity. The second output signal has third transitions of the second polarity that are simultaneous to the first transitions in the first output signal and has fourth transitions of the first polarity non-simultaneously corresponding to the second transitions in the first output signal.

Method and apparatus for generating asymmetrically deskewed complementary signals

Some of the embodiments of the present disclosure provide a D type flip-flop, comprising a first sampling module configured to sample an input signal while the input signal is at a low logical value; a second sampling module configured to sample the input signal while the input signal is at a high logical value; and a latch configured to logically generate an output signal responsively to the sampling of the input signal by the first sampling module and by the second sampling module. Other embodiments are also described and claimed.

Complementary semi-dynamic D-type flip-flop

Race free semi-dynamic D-type flip-flop

The present disclosure provides for a processor that can include digital processing circuitry that receives a digital clock signal from a supply regulated phase locked loop. The supply regulated phase locked loop can include a voltage controlled oscillator that can output an analog signal and a level restorer that can receive the analog signal from the voltage controlled oscillator and can translate the analog output into a digital signal that corresponds to an analog output of the voltage controlled oscillator. The supply regulated phase locked loop can receive an analog input having an input voltage that is within a range of acceptable input voltages. The supply regulated phase locked loop can also be configured to generate the digital output signal, such that the range of acceptable input voltages includes voltage values that are greater than and less than the output voltage.

Level-restorer for supply-regulated PLL

A frequency divider includes a first frequency divider stage coupled to a clock signal and operative to generate a first frequency divided signal. A second frequency divider stage is coupled to the clock signal and to the first frequency divider stage and is operative to generate a second frequency divided signal. A third frequency divider stage is coupled to the clock signal and to the second frequency divider stage and is configured to generate a third frequency divided signal using only i) the clock signal and ii) the second frequency divided signal so that any transition of the third frequency divided signal occurs at an edge of the clock signal at which the second frequency divided signal does not transition.

Method and apparatus for generating frequency divided signals

A phase locked loop with a charge pump circuit has increased stability and phase margin. The charge pump circuit feeds back its voltage output to generate a reference current. In one embodiment, the charge pump circuit comprises a current generator responsive to a charge voltage that has been output from the charge pump. The current generator generates a reference current based on the charge voltage and a supply voltage. The reference current may comprise a bootstrap current and an auxiliary current. The charge pump circuit also comprises a current mirror that generates a source current and a sink current that are substantially the same as the reference current. The charge pump circuit further comprises a charge voltage generator to generate the charge voltage based on the source current and the sink current. A related method is also disclosed. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.

Phase locked loop charge pump reference current bootstrapping

The disclosed technology provides a method of and an apparatus for voltage level shifting. A voltage level shifter includes two level shifting circuits and a differential amplifier. The differential amplifier forms a feedback loop with one level shifting circuit. The feedback loop controls the level shifting operation of both level shifting circuits. The differential amplifier can operate to provide a control signal that causes a level-shifted signal in the feedback loop to match a target signal. The two level shifting circuits can perform their level shifting operation based on the control signal.

Method and apparatus for controlled voltage level shifting

Level-restored for supply-regulated PLL

In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.

A CMOS comparator having a high-speed reduced-output-swing is provided. The high-speed reduced-output-swing comparator may have a fully complementary CMOS design, be self-biased, and have a rail-to-rail input common-mode range. The self-biasing scheme yields a robust comparator with a low sensitivity to temperature, processing variations, supply-voltage variations, and common-mode input voltages. The fully-complementary design leads to a physically small device with low power consumption. The rail-to-rail input common-mode range leads to a versatile comparator which may take a wide range of inputs. The high-speed reduced-output-swing allows for a quick output response to changes in the input.

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Haifa, Israel

Mel Bazes