Qualcomm Incorporated

Meital Zangvil

Sharon Graif

Lior Amarilio

Tomer Rafael Ben-Chen

Methods and apparatuses for aggregated IBIs are provided. The apparatus includes a host controller configured to communicate with at least one slave via a serial communication bus, trigger and receive a series of responses from the at least one slave via the serial communication bus, determine one response of the series of responses indicating an in-band interrupt (IBI) request, and respond to the IBI request based on a position of the one response among the series of responses. The method includes communicating with at least one slave via a serial communication bus, triggering and receiving a series of responses from the at least one slave via the serial communication bus, determining one response of the series of responses indicating an in-band interrupt (IBI) request, and responding to the IBI request based on a position of the one response among the series of responses.

Aggregated in-band interrupt based on responses from slave devices on a serial data bus line

Systems, methods, and apparatus are described. A method for data communication performed at a master device includes configuring a serial interface for a point-to-point mode of operation, transmitting a first two-bit command through the serial interface, the two-bit command including a one-bit address and a read/write bit, and initiating a transaction through the serial interface. The transaction may be identified by the two-bit command and is conducted in accordance with an I3C protocol. The transaction may include the transfer of one or more data frames formatted in accordance with the I3C protocol. The method may include receiving an acknowledgement from a slave device in response to the first two-bit command.

I3C point to point

Systems, methods, and apparatus are described. An apparatus provides a clock signal, transmits an address on a second line of the serial bus followed by a read/write bit configured to initiate a read transaction, and delays a pulse in the clock signal after transmitting the read/write bit. The pulse may be delayed for a first duration configured to accommodate a latency associated with a first slave device that is a participant in the read transaction. The apparatus may receive an acknowledgement from the first slave device while the pulse is being transmitted and may receive a first data byte from the first slave device after receiving the acknowledgment. The apparatus may stall the clock signal for a second duration after receiving the first data byte from the first slave device, and receive a second data byte from the first slave device after the acknowledgment.

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Haifa, Israel

Meital Zangvil