Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Meisei Nishikawa

Tadashi Kojima

Kazuo Konishi

Yukio Nakamura

Yasuhiro Hayashi

Toshihiko Kaneshige

Takeshi Inagaki

Jun Inagawa

Masahide Nagumo

In an interface security system between a plurality of devices mutually connected and transmitting/receiving a signal, the respective devices include respective selectors selecting a connection pattern between signals transmitted/received and external terminals for transmitting/receiving the signals and switching connections between the signals and the external terminals in accordance with a connection pattern selected, and the selectors of the respective devices select a connection pattern and switch the connections in synchronization between the respective devices.

Interface security system and method

A memory circuit having a plurality of regions. A first rearranging circuit, controlled by a control circuit, rearranges plural bits of data having different significances when a first of the regions includes a defective portion and a first one of the plural bits is to be written into the first region, so that a second of the plural bits having lower significance than that of the first bit is written into another one of the plurality of regions. A second rearranging circuit, controlled by the control circuit, rearranges the plural bits of data read out from the memory circuit so that the first and second bits are returned to correct positions.

Apparatus and method for reading and writing data

An apparatus for reproducing data stored on a disc in a plurality of tracks connected in a continuous spiral or separated in concentric tracks. The apparatus includes a device for rotating the disc, an optical pickup device aligned with one of the tracks for reading the data from the track, the pickup being subject to jump movement of alignment with the track into alignment with another track in response to movement of the device, a buffer memory device temporarily storing successive portions of the data read from the track for delaying reproduction of the data for a predetermined time after the reading of the data, a track jump detection device for detecting movement of the pickup device into alignment with anothr track and interrupting temporary storage of the data read from the other track by the buffer memory device, a drive device for moving the pickup device with respect to the disc for reading data, and for changing the alignment of the pickup device from the other track to the one track in response to the track jump detection device, and an output device for substantially uninterrupted reproduction of the temporarily stored data.

Erroneous track jump restoration apparatus for optical record disc player

A convolution arithmetic circuit has a multiplier/accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales. One memory containing the multiplicand data is periodically updated, while the other memory containing coefficient data has a storage capacity of about twice the previous memory.

Convolution arithmetic circuit for digital signal processing

A convolution arithmetic circuit has an accumulator to multiply two digital data sequences and add up the products. The sequences are stored in memories which cycle at the same rates and with different scales, the memory containing the multiplicand data being periodically updated.

High speed convolution arithmetic circuit with multiple counters

A circuit is disclosed which is applied for a digital audio disk (DAD) system for detecting a maximum inverting period of a digital audio signal optically read out from the DAD. The audio signal is prestored in the DAD so as to have the maximum and minimum inverting periods specially set by an eight to fourteen modulation (EFM). The detection circuit includes an edge detector for detecting pulse edges of the digital audio signal, a counter for counting pulse edge intervals on the basis of a modulating clock signal, a counter type register, and a comparator. When the register contents of the counter type register is smaller than the count value of the counter, the comparator produces a pulse signal by which said register updates the contents of the register by '1'. Repeating this operation, a maximum inverting period value of the digital audio signal is obtained in a fixed period of time.

Frequency detecting circuit for digital information reproducing system

The invention relates to a motor control circuit of a data reproduction apparatus, which drives a disk motor to reproduce a data signal recorded together with a sync signal on a recording medium so as to control the disk motor in accordance with a reproduced sync signal. The frequency and phase components of the reproduced sync signal are detected, and first and second motor control signals are produced in accordance with frequency and phase detection signals, respectively. A control circuit detects whether or not the frequency detection signal falls within a predetermined range. If it is determined that the frequency detection signal does not fall within the predetermined range, the second motor control signal is kept at a predetermined value.

Motor control circuit of data reproduction apparatus

The invention provides a pulse-width modulation circuit in which an output from a latch circuit for holding a count obtained by counting a reference clock signal in accordance with the period of a signal to be modulated is compared by a comparator with an output from a ramp counter for counting the reference clock signal at a predetermined period so as to perform a pulse-width modulation. The number of bits of the comparator and the ramp counter is decreased by n bits with respect to the number N (N&gt;n) of bits of the latch circuit.

Pulse-width modulation circuit

A phase locked loop control circuit for a digital audio disk system is disclosed which has a voltage-controlled oscillator (VCO), a reference signal generator for generating a reference signal corresponding to the phase state of a digital audio signal when the digital audio signal is reproduced or read out and which is recorded on a digital audio disk (DAD) to have a maximum or minimum inverting period value predetermined by the eight to fourteen modulation method, a phase comparator connected to the output terminal of the reference signal generator and the VCO, a detector for detecting the maximum inverting period value included in the digital audio signal; and an adder for adding outputs from the phase comparator and the detector and for supplying a sum result as an oscillation control signal to the VCO.

Growing community of inventors

Musashino, Japan

Meisei Nishikawa