Qualcomm Incorporated

National Semiconductor Corporation

Intel Corporation

Meir Tsadik

Assaf Touboul

Gideon Intrater

Oved Oz

Shay Landis

Gideon Shlomo Kutz

Michael Levitsky

Ran Berliner

Igor Gutman

Yachin Afek

Israel Greiss

Shmuel Vagner

Amos Intrater

Lev Epstein

Iddo Carmon

Omri Viner

Moshe Doron

Alberto Sandbank

Ronny Cohen

Lior Katzri

Raya Levitan

Ilan Shimony

Zvi Greenfeld

Yehezkel Tzadik

Itael Fraenkel

Andy Birenbaum

Sidi Yomtov

Ron Gabor

Maxim Gotman

Albert Yosher

Nathaniel Leibowitz

Moshe Tanach

Eran Richardson

Yoram Kulbak

In order to enable asynchronous, autonomous reception beam switching at a UE while minimizing degradation due to a transient in link performance, a method, apparatus, and computer-readable medium for wireless communication are provided. The apparatus receives CSI-RS on different reception beams in different symbols, wherein one reception beam being a current serving reception beam, and determines whether to switch to a different reception beam based on a SPEFF metric for the different reception beam and/or a severity of a potential link transient qualified in terms of the expected CQI/MCS degradation in the channel. The apparatus may switch from a current serving reception beam to a second reception beam when a first channel quality for the current serving reception beam is within a threshold value of a second channel quality for the second reception beam, the second channel quality being measured using a current configuration.

Autonomous reception beam refinement and tracking

Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.

Method and apparatus for wireless broadband systems direct data transfer

Inter-processor communication (IPC) apparatus and a method for providing communication between two processors having a shared memory, the IPC apparatus including an arbitrated bus coupling the processors to one another and to the memory, a buffer in the shared memory associated with each processor, and at least one pair of First In First Out hardware units (FIFOs) coupled to each processor, the FIFOs holding pointers to addresses in the buffer associated with that processor, wherein a first of the pair of FIFOs (an empty buffer FIFO) is configured to hold pointers to empty portions of the buffer while the second of the pair of FIFOs (a message FIFO) is configured to hold pointers to portions of the buffer having data therein.

Inter-processor communication apparatus and method

A method and system for processing LLRs, in a receiver, of transmissions over a wireless telecommunication system, the method including receiving multiple soft symbols, selecting a set of appropriate instructions for LLR calculation for the soft symbols, arranging the soft symbols in a register of a processor according to the selected instructions, selecting an appropriate single instruction from the set of instructions to be implemented by the processor using the soft symbols in the register as operands, and calculating, by a computation unit, multiple LLR values for the multiple soft symbols, in parallel, by means of the selected instruction.

Advanced LLR processor for wireless telecommunication system

An embodiment of the present invention is a technique to simulate performance of a multi-core system. A micro-architecture effect is estimated from each core in the multi-core system. A model of a memory hierarchy associated with each core is simulated. The simulated model of the memory hierarchy is superpositioned on the estimated micro-architecture effect to produce a performance figure for the multi-core system.

Performance simulation of multiprocessor systems

The central processing unit of an integrated circuit data processing system includes both means for processing a first non-maskable interrupt (NMI) request received by the data processing system on a first NMI request line and means for processing a second NMI request received by the data processing system on a second NMI request line different from the first NMI request line and within a predefined time period after receipt of the first NMI request. Both. NMI requests are serviced by the data processing system even if the second NMI request is received prior to completion of processing of the first request.

Mechanism for handling non-maskable interrupt requests received from

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

Integrated data processing system including CPU core and parallel,

An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The OP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

Integrated CPU core and parallel, independently operating DSP module and

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Hod Hasharon, Israel

Meir Tsadik