Cadence Design Systems, Inc.

Meir Ovadia

Rodion Vladimirovich Melnikov

Marat Teplitsky

Efrat Gavish

Yonatan Ashkenazi

Manu Chopra

Steven Guy Esposito

Kalev Alpernas

Matan Vax

Jonathan Lee DeKock

Talia Leah Orztizer

Swaminathan Venkateasan

Erez Singer

Rodion Milnikov

Noa Gradovich

A method includes generating on a host machine a validated verification test scenario comprising a graph defining a scheduled performance order of a plurality of actions to be performed on a DUT and a corresponding verification environment; obtaining a subset of one or more actions to be added to the validated scenario while maintaining the plurality of actions of the validated scenario and the scheduled performance order, forming an amended verification test scenario; and applying a runtime solver in a target language of the DUT and the corresponding verification environment on the amended verification test scenario to generate a test in a target code and to apply the test on the DUT and the corresponding verification environment wherein inclusion of any of said one or more actions or an order of performance of said one or more actions of the subset in the test is determined at runtime.

Method and system for generating verification tests at runtime

A method for automatically finding a verification test of a plurality of verification tests that were executed in a verification process of a design under test (DUT) that satisfies a criterion, may include using a processor, obtaining from a user a criterion that relates to one or more test actions; using a processor, obtaining a log with logged execution data that includes start and end times for each action of each of the tests of the plurality of verification tests during an execution run of that test; and for each test of the plurality of verification tests, using a processor, determining from the logged data whether that test satisfies the obtained criterion, and if a test of the plurality of verification tests was determined to satisfy the obtained criterion, using a processor, executing that test on the DUT.

Method and system for generating a validation test

A method for generating a validation test for testing an electronic design may include using a processor, analyzing a plurality of actions of a validated scenario to identify an executable corresponding to each of the actions and to identify one or a plurality of variables referred to by each of the actions; using a processor, identifying actions in said plurality of actions that correspond to different executables of the identified executables but refer to a same variable of said one or a plurality of variables that is to be written to or read from a shared memory assigned to the different executables; and using a processor, generating a test code for the validated scenario that includes one or a plurality of access protection commands to manage access by the identified actions that correspond to the different executables and refer to the same variable.

A method for debugging a system on chip (SoC) under test, may include automatically inserting commands in a test code for testing the SoC for invoking printing of messages of data, each message of the messages including start time, end time of each executed action of a plurality of actions, the executed action to be invoked by the test code when testing the SoC, the data further including identity of a processing component of a plurality of processing components of the SoC, on which the executed action was executed; recording the data of the invoked printed messages during testing of the test code on the SoC; and displaying, via a graphical user interface, one or a plurality of graphical representations, each of said graphical representations relating to a period of activity of one of the plurality of processing components over time, based on the recorded data.

Method and system for profiling performance of a system on chip

A method for processing verification tests for testing a design under test (DUT), may include receiving from a user a start time message and an end time message for each action of actions in a verification test in a target code form, to be printed into a log file of an execution of the test, so as to list chronologically the start time and end time of each of the actions in the log file. The method may also include executing the verification test to obtain the log file with the start time and end time messages and, using a processor, analyzing the log file to construct a graph representation of the validation test, based on the printed start and end times of the actions of the test.

Method and system for processing verification tests for testing a design under test

A method for reconstructing a graph representation of a previously executed verification test, may include obtaining a truncated chronicle of start time and end time messages of actions of the verification test that were logged during execution of the verification test on a design under test (DUT); using a processor, parsing and analyzing the start time and the end time messages to determine an order of the actions; using a processor, determining an order of other actions of said verification test, based on a graph representation of a verified scenario from which the verification test was generated; and reconstructing the graph representation of the verification test based on the determined order of the actions and order of the other actions.

Method and system for reconstructing a graph presentation of a previously executed verification test

A method for automated selection of a subset of a plurality of validation tests for testing a device under test (DUT), may include obtaining the plurality of validation tests; using a processor, obtaining from a user, via an input device, one or a plurality of conditions relating to one or a plurality of execution parameters; and using a processor, analyzing each of the validation tests to identify a subset of the validation tests that includes verification tests conforming to said one or a plurality of conditions.

Method and system for automated selection of a subset of plurality of validation tests

A method for generating a validation test, may include obtaining, using a processor, a validated scenario for generating a test for a verification model, the validated scenario represented in the form of a directed acyclic graph with a plurality of actions as nodes of the graph. The method may also include analyzing, using the processor, the graph to identify an action of said plurality of actions designed to be executed on a thread that is associated with a faulty scheduler of a verification model to be tested. The method may further include, upon identifying the identified action, amending, using the processor, the verified scenario by removing the identified action from the graph.

Method and system for generating validation tests

A method for generating a validation test may include using a processor, identifying, in a scenario for validation testing, a plurality of actions that address a single resource in a conflicting manner; and automatically generating target code of the scenario that includes one or a plurality of resource management commands so as to prevent conflicting addressing of that resource by said plurality of actions.

The present disclosure relates to systems and methods for performing out of order name resolution in an electronic design language. Embodiments may include receiving, one or more design units associated with an electronic design and registering the one or more design units in a registry database. Embodiments may further include performing local name resolution for each element reference within at least one of the one or more design units. In response to registering, embodiments include identifying at least one element reference upon which local name resolution was not performed and obtaining an appropriate element reference from the registry database. Embodiments may further include reviewing at least one secondary design unit for one or more local declarations and performing local name resolution for one or more remaining element references using a design hierarchy.

System and method for performing out of order name resolution in an electronic design

A method for generating a minimized combined scenario for use in simulation, from a post-silicon validation test that includes a combined scenario, may include obtaining a failed scenario loop of a scenario of the combined scenario that includes combined action scenarios that were executed in loops during a post-silicon validation test of a system on chip; and adding any loops of other scenarios of the combined scenario that were executed at least partially concurrently with the failed scenario loop, while discarding any loops of other scenarios of the combined scenario that were completed during the post-silicon validation test before the failed scenario loop or did not commence before the failed scenario loop was completed.

Method and system for generating post-silicon validation tests

A method and system for debugging memory allocation and memory release may include recording execution events of an execution run of a program including data related to objects pertaining to that program, and data related to object association pertaining to that program at a plurality of points in time. The method may also include receiving via a user interface a user selection of an object of said objects. The method may further include identifying one or a plurality of pointers pointing from one or a plurality of objects at the selected object based on the recorded data related to object association and finding one or a plurality of execution events of said execution events corresponding to assignments of said one or a plurality of pointers. The method may further include distinctly marking a portion of the code, presented to the user on a display device, representing said one or a plurality of execution events that correspond to assignments of said one or a plurality of pointers.

Method and system for automated debugging memory allocation and memory release

A method for generating a post-silicon validation test for a system on chip (SOC), may include obtaining a selection of action scenarios from a set of scenarios originally constructed for generating simulation tests; combining the selected scenarios into a combined scenario in which the selected scenarios are to be executed in parallel; and generating a post-silicon test code corresponding to the combined scenario.

A method for debugging a system on chip (SoC) under test, the method may include executing a test code on the SoC, the test code designed to invoke a plurality of actions; recording output data from the SoC resulting from the executed test code; linking between actions detected in the recorded output data and actions of the plurality of actions of the test code by identifying a start and an end times of each of the detected actions in the recorded output data, and associating the identified start and end times with a start and an end times of actions of the plurality of actions of the test code; and causing display, via a graphical user interface, of a waveform representation of the detected actions over time, a representation of the test code and a representation of the output log.

Method and system for debugging a system on chip under test

A method for automatically generating executable system-level tests may include receiving scenario information for testing a device under test (DUT). The method may also include analyzing the scenario information to determine whether there is a legal order in which some or all actions included in the test are to be executed by a plurality of processors of the DUT requiring that one or a plurality of the actions be performed before one or a plurality of other actions may be performed; and identify necessary communications between the processors relating to synchronization points between them. The method may further include automatically generating a test that includes a plurality of actions performed by some or all of the processors in compliance with the legal order.

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Rosh Ha-Ayin, Israel

Meir Ovadia