Chip Express (israel) Ltd.

Quick Technologies Ltd.

Elron Electronic Industries Ltd.

Other

Chip Express Corporation

Meir I Janai

Zvi Orbach

Uzi Yoeli

Eran Rotem

Gideon Amir

Alon Kapel

Michael Stephen Silverstein

Sharon Zehavi

Yoram Cassuto

Configurable cell for customizable logic array device

An integrated circuit coated with a layer of plasma deposited polymer which is ablatable by visible light laser radiation. The plasma layer is deposited on the circuit in a plasma chamber and the layer is ablated at selected locations.

Laser ablateable material

A customizable logic array device including an array of identical multiple input, function selectable logic cells comprising a first conductive layer, application configurable interconnection apparatus selectably interconnecting the multiple input, function selectable logic cells, the application configurable interconnection apparatus comprising at least two conductive layers.

Customizable logic array device

This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.

Mapping of gate arrays

A very high speed customizable logic array device comprising:

High speed customizable logic array device

Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.

Customizable three metal layer gate array devices

Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

Personalizable gate array devices

A personalizable multi-chip carrier including a substrate, first and second pluralities of conductors arranged on respective first and second parallel planes, the first and second pluralities of conductors defining a grid of conductors arranged over the substrate and defining a multiplicity of crossing locations at which conductors of the first and second pluralities cross each other, apparatus for interconnecting the first and second pluralities of conductors at locations adjacent the multiplicity of crossing locations and including a plurality of fusible links.

Personalizable multi-chip carrier including removable fuses

An active matrix of a display panel having a plurality of array elements and at least two data busses, each array element including a primary switch initially connected to the data busses and at least one connectable secondary switch, wherein, when the primary switch is disconnected from the busses, one of the at least one secondary switches is connected to the busses.

Active matrix display panel having connectable secondary switches

A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.

Ablative etch resistant coating for laser personalization of integrated

An integrated circuit which is readily customized by the user to his specific requirements and is thus suitable for prototype and small scale production.

Fabrication of personalizable integrated circuits

A selectably customizable semconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from the first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship, the first metal layer including a plurality of fusible conductive bridges joining adjacent pairs of the first elongate strips, the fusible conductive bridges including first and second fusible links, the first metal layer also including a plurality of branch strips, each branch strip connecting one of the fusible conductive bridges at a location intermediate the first and second fusible links to a branch overlap location spaced from the multiplicity of elongate strip overlap locations, an electrical connection being formed between the first metal layer and the second metal layer at each of the branch overlap locations.

Customizable semiconductor devices

A technique for providing a radiation formable conductive link in an integrated circuit comprising the steps of: depositing a plurality of aluminum conductors on an exposed surface of an otherwise completed integrated circuit, and forming a bridge of amorphous silicon layer joining the aluminum conductors at selected locations, whereby subsequent laser radiation produces diffusion of aluminum into the amorphous silicon, producing a highly conductive aluminum doped silicon bridge.

Integrated circuits and a method for manufacture thereof

A selectably customizable semiconductor device first and second metal layers disposed in respective first and second planes and including respective first and second elongate strips, conductive branches being provided in association with the elongate strips.

Growing community of inventors

Haifa, Israel

Meir I Janai