Sandisk Il Ltd.

M-Systems Flash Disk Pioneers, Ltd.

Msystems Ltd.

Meir Avraham

Menahem Lasser

Amir Ronen

Itai Dror

Dan Inbar

Ziv Paz

Boris Dulgunov

Eliyahu Fumbarov

A plurality of memory cells are managed by obtaining values of one or more environmental parameters of the cells and adjusting values of one or more reference voltages of the cells accordingly. Alternatively, a statistic of at least some of the cells, relative to a single reference parameter that corresponds to a control parameter of the cells, is measured, and the value of the reference voltage is adjusted accordingly. Examples of environmental parameters include program-erase cycle count, data retention time and temperature. Examples of reference voltages include read reference voltages and program verify reference voltages. Examples of statistics include the fraction of cells whose threshold voltages exceed initial lower bounds or initial medians.

Drift compensation in a flash memory

A method includes storing at a non-volatile memory in a data storage device a first copy of a memory management table. The method further includes storing, at the non-volatile memory, a list of data entries that identify unused blocks of the non-volatile memory, where the list defines an order of allocating the unused blocks. The method further includes, in response to detecting a power event, accessing an entry of the ordered list to identify a block, and selectively updating the first copy of the memory management table based on a status of the identified block.

Method and apparatus for facilitating fast wake-up of a non-volatile memory system

Methods for maintaining data structures in accordance with the events of a nonvolatile memory system. At least part of one or more management tables and a future information data structure are stored in a nonvolatile memory. The future information data structure contains records of events expected to occur subsequent to the storing of the future information data structure. When flash memory events occur, those events are handled in accordance with the future information data structure. When the memory system wakes up, the management table(s) is/are retrieved and the records of the future information data structure are compared with the table(s) state. The table(s) is/are updated in accordance with the future information data structure.

Method and system for facilitating fast wake-up of a flash memory system

A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.

SDRAM memory device with an embedded NAND flash controller

A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.

System-in-package and method of testing thereof

Systems and computer readable codes for maintaining data structures in accordance with the events of a nonvolatile memory system. At least part of one or more management tables and a future information data structure are stored in a nonvolatile memory. The future information data structure contains records of events expected to occur subsequent to the storing of the future information data structure. When flash memory events occur, those events are handled in accordance with the future information data structure. When the memory system wakes up, the management table(s) is/are retrieved and the records of the future information data structure are compared with the table(s) state. The table(s) is/are updated in accordance with the future information data structure.

A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, and where rapid decoding is important. The present invention arranges the data to be protected into a rectangular array and determines the location of a single bit error in terms of row and column positions. So doing greatly reduces the size of lookup tables for converting error syndromes to error locations, and allows fast error correction by a simple circuit with minimal hardware allocation. Use of square arrays reduces the hardware requirements even further.

Compact high-speed single-bit error-correction circuit

A datum is stored in a memory by placing a memory cell in a first state that is indicative of the datum, and later placing the same or a different cell in a second state that is indicative of the same datum. If a different cell is placed in the second state, both cells are programmed to store the same number of bits, and then preferably the first cell is erased. Preferably, the first cell is placed in the first state by the application thereto of a first train of voltage pulses until the cell's threshold voltage exceeds a first reference voltage, and the first or second cell is placed in the second state by the application thereto of a second train of voltage pulses until the cell's threshold voltage exceeds a second reference voltage.

Two-phase programming of a flash memory

An appliance that includes a host device and a memory unit with a primary memory, and a method of operating the appliance. According to one aspect of the appliance, the primary memory is nonvolatile and the memory unit also includes a volatile memory a power sensor and a controller. When the power sensor detects interruption of power to the memory unit, the controller copies data selectively from the volatile memory to the primary memory. Power for this copying is provided by a secondary power source such as a battery or a capacitor. According to another aspect of the appliance, the appliance includes primary and secondary power sources, and the memory unit also includes a charge pump whose functions include both boosting power from the primary source for the primary memory and charging the secondary source.

Appliance, including a flash memory, that is robust under power failure

A method of managing the erasure of units of a flash memory. An indication is provided that an erasure of one or more units is pending, either before the units are erased or, in case of power loss, during the erasure. Subsequent to a completed erasure, an indication provided before an erasure is either erased or offset by an indication of a completed erasure. Upon powering up, or, in some embodiments, also prior to writing, the indications are inspected and units not completely erased are erased again. The present invention may be implemented in hardware, in firmware, in software, or in any combination of the three. In embodiments not totally reliant on software, appropriate non-volatile registers are provided, for storing the indications as erase pending flags and erase completed flags, and also for storing corresponding unit numbers.

Detecting partially erased units in flash devices

A device, a method and a system for reading/writing data, preferably of a particular type, from a first dedicated port of a NVM storage, while other data is reading/written to at least a second general port of the NVM storage. Preferably, while data is being continually read/written through the dedicated port of the NVM storage, the logic processor which controls the NVM storage optionally &ldquo;sleeps&rdquo;, or reverts to a lower power consumption mode. The NVM storage of the present invention may optionally feature a plurality of ports, as long as at least one dedicated port for reading/writing data, preferably of a particular type, and at least one general port for reading/writing data, is provided. According to preferred embodiments of the present invention, the at least one dedicated ports is a port for reading/writing streamed data, such as streaming audio and/or video data for example.

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Rishon Lezion, Israel

Meir Avraham