International Business Machines Corporation

MeiKei Leong

Min Yang

Edward J Nowak

Brent A Anderson

Diane Catherine Boyd

Thomas Safron Kanarsky

Jakub Tadeusz Kedzierski

Alexander Reznicek

Bruce Bennett Doris

Cyril Cabral, Jr

Paul Michael Solomon

Chun-Yung Sung

Victor Chan

Rajesh Rengarajan

Victor W C Chan

Ricky S Amos

John Michael Hergenrother

Massimo V Fischetti

Katayun Barmak

Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

Method of forming an integrated circuit structure on a hybrid crystal oriented substrate

The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

Hybrid planar and FinFET CMOS devices

The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a &#x3c;110&#x3e; crystal orientation and a biaxial compressive strain. The term 'biaxial compressive stress' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing &#x3c;110&#x3e; layer; and creating a biaxial strain in the silicon-containing &#x3c;110&#x3e; layer.

Enhancement of electron and hole mobilities in &#x3c;110&#x3e; Si under biaxial compressive strain

An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a &#x3c;001&#x3e; direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a &#x3c;110&#x3e; direction and the at least one NFET has a current flow in a &#x3c;100&#x3e; direction. The &#x3c;110&#x3e; direction is perpendicular to the &#x3c;100&#x3e; direction. A method of fabricating such as integrated semiconductor structure is also provided.

Substrate engineering for optimum CMOS device performance

High mobility plane CMOS SOI

Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

Method and process to make multiple-threshold metal gates CMOS technology

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Wappingers Falls, NY, United States of America

MeiKei Leong