Globalfoundries U.S. Inc.

Mei Yu Soh

Santosh Sharma

A GaN logic circuit may include an input node receiving an input voltage, a first pull up transistor pulling up an output voltage in response to the input voltage, and a first depletion mode transistor having a first gate to which a first gate voltage is applied and a second gate to which a second gate voltage is applied. The first depletion mode transistor may control the first pull up transistor in response to a gate voltage difference between the first gate voltage and the second gate voltage. The logic device may further include a capacitor having a first end coupled to the first depletion mode transistor and a second end coupled to the first pull up transistor.

Charge pumps, logic circuits including charge pumps, logic devices including logic circuits, and methods of operating logic circuits

A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

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Singapore, Singapore

Mei Yu Soh