Applied Materials, Inc.

Mei-Yee Shek

Li-Qun Xia

Mihaela A Balseanu

Hichem M'Saad

Srinivas D Nemani

Mehul B Naik

He Ren

Weifeng Ye

Ellie Y Yieh

Derek R Witty

Vladimir Zubkov

Kelvin Chan

Yong Cao

Kang Sub Yim

Bhargav S Citla

Jia Lee

Yu Jin

Isabelita Roflox

Christopher Dennis Bencher

Alexandros T Demos

Michael Santiago Cox

Judy H Huang

Amir Hamed Al-Bayati

Chentsau Chris Ying

Naomi Yoshida

Jingmei Liang

Martin Jay Seamons

Kaushal Kishore Singh

Nikolaos Bekiaris

Tzu-Fang Huang

Rongping Wang

Victor Nguyen

Yana Cheng

Joe Feng

Xiaolan Ba

Sree Rangasai V Kesapragada

Shi You

Chris Ngai

Juan Carlos Rocha-Alvarez

Steven Verhaverbeke

Sanjeev Baluja

Deenesh Padhi

Thomas E Nowak

Roman Gouk

Bencherki Mebarki

Huiwen Xu

Scott A Hendrickson

Minrui Yu

Prahallad Iyengar

Khaled A Elsheref

Jethro Tannos

Joshua Rubnitz

Maximillian Clemons

Ritwik Bhatia

Yong-Won Lee

Troy Kim

Lipan Li

Xiaojun Zhang

Isabelita Rolfox

Vladamir Zubkov

Maximilian Clemons

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

Method of dielectric material fill and treatment

The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

High pressure annealing process for metal containing materials

Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450&#xb0; C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom

Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R, R, R, R, R, R, R, R, R, R, R, and Rare independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Silicon carbonitride gapfill with tunable carbon content

Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10&#xb0; and about 50&#xb0;.

Methods of forming metal silicide layers and metal silicide layers formed therefrom

A method for forming a thermally stable spacer layer is disclosed. The method includes first disposing a substrate in an internal volume of a processing chamber. The substrate has a film formed thereon, the film including silicon, carbon, nitrogen, and hydrogen. Next, high pressure steam is introduced into the processing chamber. The film is exposed to the high pressure steam to convert the film to reacted film, the reacted film including silicon, carbon, oxygen, and hydrogen.

Method to fabricate thermally stable low K-FinFET spacer

An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.

Dielectric/metal barrier integration to prevent copper diffusion

Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer.

Cu/barrier interface enhancement

An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Embodiments described herein generally relate to the formation of a UV compatible barrier stack. Methods described herein can include delivering a process gas to a substrate positioned in a process chamber. The process gas can be activated to form an activated process gas, the activated process gas forming a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen. The activated process gas can then be purged from the process chamber. An activated nitrogen-containing gas can be delivered to the barrier layer, the activated nitrogen-containing gas having a N:NHratio of greater than about 1:1. The activated nitrogen-containing gas can then be purged from the process chamber. The above elements can be performed one or more times to deposit the barrier stack.

Enhancing electrical property and UV compatibility of ultrathin blok barrier film

Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer.

Cobalt selectivity improvement in selective cobalt process sequence

Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Methods for forming passivation protection for an interconnection structure

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Palo Alto, CA, United States of America

Mei-Yee Shek