Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Other

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Univ. of Singapore

Chartered Semiconductor

Nanyang Technology Univ.

Mei Sheng Zhou

Simon Yew-Meng Chooi

Subhash Gupta

Yi Liang Xu

John Leonard Sudijono

Sudipto Ranendra Roy

Yakub Aliyu

Paul Kwok Keung Ho

Liang Choo Hsia

Paul Kwok Ho

Xu Yi

Alex K H See

Yelehanka Ramachandramurthy Pradeep

Hai Cong

Jinping Liu

Eng Hua Lim

Elgin Kiok Quek

Jia Zhen Zheng

Daniel Yen

Jian Xun Li

Siu Choon Ng

Kwok Keung Paul Ho

Joseph Zhifeng Xie

Christopher Lim

Hardy Chan

Licheng Han

Lap Chan

Huang Liu

Alex See

Wei Lu

Chew Hoe Ang

Henry Gerung

Randall Cha

Ron-Fu Chu

Wen Jun Liu

Benjamin Colombeau

Jin Ping Liu

Pradeep Yelehanka

Wenhe Lin

Francis Lionel Benistant

Ramasamy Chockalingam

Yun Ling Tan

Jie Yu

Hui Peng Koh

Vijai Kumar Chhagan

Pei Ching Lee

Jianxun Li

Debora Chyiu Hyia Poon

Binbin Zhou

Jianhui Ye

Qing Hua Zhong

Jeff Jianhui Ye

Jian Hui Ye

Li-Jui Chen

Cheng-Lin Huang

Yang Pan

Chung-Long Chang

Kin Leong Pey

Chun-Hsien Lin

Ying Keung Leung

Sang Yee Loong

Yu-Liang Lin

Chim Seng Seet

Randall Cher Liang Cha

Henry Lo

Chung Woh Lai

Bei Chao Zhang

Ai-Sen Liu

Zheng Zou

Sangki Hong

Chun Hui Low

Chew-Hoe Ang

Ganesh S Samudra

Bo Yu

Qun Ying Lin

Peter Chew

Chivukula Subrahmanyam

Chee Tee Chua

Raymond Joy

Xin Wei Zhang

Alex Kai Hung See

Chiew Wah Yap

Arthur Ang

Wen Zhan Zhou

Zhong Dong

Chockalingam Ramasamy

Kok Hiang Tang

Zainab Ismail

Chyiu Hyia Poon

Vincent Sih

Ping Yu Ee

Young-Tong Tsai

Xue Chun Dai

Tak Yan Tse

Vijai Komar Chhagan

Han Guan Chew

Chyi Shyuam Chern

Yuan-Ping Lee

Calvin Leung Chor

Sheau-Tan Loong

A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

Strained channel transistor structure and method

A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.

Integrated circuit and method of fabrication thereof

A method for fabricating a semiconductor device is provided. The method comprises selectively forming a first layer over a first and second exposed portions of a substrate. The first and second exposed portions are of different sizes and are located adjacent to a first and second active devices. During the first layer formation, a gas mixture comprising first and second source gases that function as growth components for forming the first layer and a reactant gas that functions as an etching component for controlling selectivity of the first layer growth is provided. The reactant gas is different from the first and second source gases and one of first and second source gases forms the first layer at a faster rate over the first exposed portion as compared to the second exposed portion and the other source gas exhibits an opposite behavior.

Methods for reducing loading effects during film formation

A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Processing with reduced line end shortening ratio

A composite etch stop layer which comprises primary and secondary stop layers is used to form contacts in a dielectric layer to contact regions in a substrate. The secondary etch stop layer includes a high-k dielectric material to achieve high etch selectivity with the dielectric layer during contact formation. The secondary stop layer is removed to expose the contact regions. Removal of the secondary stop layer is achieved with high selectivity to the materials therebelow.

Method of forming high-k dielectric stop layer for contact hole opening

The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing

A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (Rvalue) represents the accuracy index of the MTUT.

Multi-variable regression for metrology

A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.

Method for reducing silicide defects in integrated circuits

Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.

Damascene contact structure for integrated circuits

A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching is provided by monitoring the removal of the endpoint detection layer. The endpoint detection layer is formed on a surface of an etching apparatus that is exposed to the same etching conditions as the thin film to be etched. The etching of the thin film is stopped when a predetermined amount of the endpoint detection layer has removed from the surface of the etching apparatus.

Thin film etching method and semiconductor device fabrication using same

Growing community of inventors

Singapore, Singapore

Mei Sheng Zhou