Pfc Device Corporation

Pfc Device Holdings Limited

Nan Ya Plastics Corporation

Invinci Semiconductor Corporation

Mei-Ling Chen

Hung-Hsin Kuo

Kuo-Liang Chao

Kou-Liang Chao

Tse-Chuan Su

Lung-Ching Kao

Kuan-Yu Chen

Paul Chung-Chen Chang

Ming-Jen Tzou

Chi-Cheng Chen

Hsu-Heng Lee

Yi-Lun Hsia

Li-Ming Chang

Chung-Chen Chang

A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region. The device electrode is located in a device trench in the active region, and is electrically isolated from the epitaxial layer and the contact metal layer. The first termination electrode is located in a first termination trench in the termination region and is electrically isolated from the epitaxial layer. The second termination electrode is located at a bottom of the first termination trench and is electrically isolated from the first termination electrode and the epitaxial layer. Both the first termination electrode and the second termination electrode are capable of being selectively floating.

Power semiconductor device and manufacturing method thereof

A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

Trench schottky rectifier device and method for manufacturing the same

A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.

MOS P-N junction diode with enhanced response speed and manufacturing method thereof

Trench Schottky rectifier device and method for manufacturing the same

A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as poly-silicon structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

A low-temperature epitaxial method manufactures backside field stop layer of insulated gate bipolar transistor (IGBT) first provides a first conductive type substrate and fabricates front-side elements and front metal layer on a front side of the IGBT. A second conductive type impurity layer is formed on a back side of the first conductive type substrate by low-temperature epitaxial process and a collector metal layer is formed on bottom face of the first conductive type substrate.

Low-temperature epitaxial method for manufacturing backside field stop layer of insulated gate bipolar transistor (IGBT)

A low-temperature oxide method is used for manufacturing backside field stop layer of IGBT and first fabricates front elements and front metal layer on a first face of a first conductive type substrate. A multiple-recesses structure is formed on a back side of the first conductive type substrate. Each of the recess in the multiple-recesses structure has first conductive type implanted patterns on exterior sides thereof and the multiple-recesses structure has a first conductive type implanted layer on bottom thereof. A plurality of first conductive type polysilicon layers are deposited into the multiple-recesses structure and respectively corresponding to the first conductive type implanted patterns. A second conductive type impurity layer is formed on the bottom of the first conductive type substrate and laser annealing is conducted to form backside field stop layer for IGBT.

Low-temperature oxide method for manufacturing backside field stop layer of insulated gate bipolar transistor

A method of manufacturing super junction for semiconductor device is disclosed. The super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Method of manufacturing super junction for semiconductor device

A super junction for semiconductor device includes a silicon substrate with a first conductive type epitaxial layer, a plurality of highly-doped second conductive type columns formed in the first conductive type epitaxial layer, and a plurality of lightly-doped (first conductive type or second conductive type) side walls formed on outer surfaces of the highly-doped second conductive type. The semiconductor device is super-junction MOSFET, super junction MOSFET, super junction Schottky rectifier, super junction IGBT, thyristor or super junction diode.

Super junction for semiconductor device and method for manufacturing the same

A trench MOS PN junction diode structure includes a first conductive type substrate, a plurality of trenches defined on a face of the first conductive type substrate, a gate oxide layer formed at least on inner sidewalls of the trenches, a polysilicon layer formed in the trenches, a second conductive type low-concentration ion-implanted region formed at least in the first conductive type substrate, a high-concentration ion-implanted region formed below the trenches, and an electrode layer covering the first conductive type substrate, the second conductive type low-concentration ion-implanted region, the gate oxide and the polysilicon layer. The high-concentration ion-implanted region below the trenches provides pinch-off voltage sustention in reversed bias operation to reduce leakage current of the trench MOS PN junction diode structure.

Trench MOS PN junction diode structure

A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a polysilicon oxide layer, a central conductive layer, ion implantation layer, a channel region, and a metallic sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer, and a polysilicon oxide layer formed on the polysilicon structure. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. An ion implantation layer is formed within the guard ring and the central conductive layer. Afterwards, a metallic sputtering layer is formed, and the mask layer is partially exposed.

A high-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor (IGBT) includes a first conductive type substrate, a plurality of trenches defined on a bottom face of the substrate, a plurality of first conductive type doping regions formed on bottom face of the trenches, a second conductive type doping region formed on bottom face of the substrate, and a first conductive type field stop doping region formed in the substrate and separated from the bottom face of the substrate by a field stop depth, where the field stop depth is larger than a depth of the trench. Due to a separation between the first conductive type doping regions and the second conductive type doping region, Zener diode can be prevented from forming on bottom side of the substrate and the performance of IGBT can be accordingly enhanced.

High-performance reverse-conduction field-stop (RCFS) insulated gate bipolar transistor and method for manufacturing the same

A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Growing community of inventors

Taipei, Taiwan

Mei-Ling Chen