Realtek Semiconductor Inc.

Mei-Chuan Lu

Jeong-Fa Sheu

Chen-Kuo Hwang

Ming-Kai Chuang

Wei-Chung Cho

Chia-Kuei Hsu

A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.

Test circuit

A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

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Taichung, Taiwan

Mei-Chuan Lu