International Business Machines Corporation

Mehulkumar Patel

Venkatesh Sainath

Vaidyanathan Srinivasan

Srinivas Kotta

Nitin Kumar Gupta

Deepak Chandrashekhar Shetty

Guha Prasad Venkataraman

Manish Mukul

Vishnupriya R

Krishna P Prabhu

Saravanan Sethuraman

Aspects of the invention include identifying a first subsystem and a second subsystem of a plurality of subsystems respectively storing a first compressed data and a second compressed data, wherein the first compressed data and the second compressed data are fragments of a requested data. A compression method used to compress the first compressed data and second compressed data is identified. A first accelerator of first subsystem and a second accelerator of the second subsystem is identified. The first compressed data from a first local memory of the first subsystem is offloaded to the first accelerator, and the second compressed data from a second local memory of the second subsystem is offloaded to the second accelerator, wherein offloading comprises provided a decompression method for the first compressed data and the second compressed data.

Accelerate memory decompression of a large physically scattered buffer on a multi-socket symmetric multiprocessing architecture

Method and apparatus for managing memory includes collocating electronic persistent memory along with a primary memory on a memory module. The electronic persistent memory and the primary memory may communicate via a module local bus comprising a plurality of memory channels. A data migration protocol may be used over a memory channel of the plurality of memory channels to copy data from the electronic persistent memory to the primary memory, and the data may be accessed from the primary memory. The combination of electronic persistent memory and primary memory (e.g. DRAM) in a single memory module with module local bus having a device controller running firmware is one implementation of storage class memory (SCM).

Block input/output (I/O) accesses in the presence of a storage class memory

Embodiments herein describe using compression engines in a processor subsystem to compress only the data fragments stored locally. That is, an application may be allocated a buffer where the physical memory of that buffer is spread across multiple processor subsystems. Rather than asking a single actor (e.g., a single host processor or compression engine) to compress all the fragments of the buffer, a compression library can instead instruct the individual compression engines in each of the processor subsystems to compress only the fragments stored in local memory in the same processor subsystem. Doing so leverages the memory affinity between the compression engines in the local memory which can reduce the overall time required to perform compression.

Accelerating memory compression of a physically scattered buffer

Reconfiguring processing groups for cascading data workloads including receiving a request to reconfigure a computing system to execute a workload, wherein the computing system comprises a first processing group and a second processing group, wherein the first processing group comprises a first central processing unit (CPU), a first graphics processing unit (GPU), and a second GPU, and wherein the second processing group comprises a second CPU and a third GPU; reconfiguring the computing system including activating a processor link spanning the first processor group and the second processor group between the second GPU and the third GPU; and executing the workload using the first GPU, second GPU, and third GPU including cascading data, via processor links, from the first CPU to the first GPU, from the first GPU to the second GPU, and from the second GPU to the third GPU.

Reconfiguring processing groups for cascading data workloads

An adapter is configured to connect to a network. The adapter including a controller configured to receive a stream of network communication from a computer system physically connected to the adapter. The controller is further configured to detect a first identifier. The first identifier is related to a first communication unit of the stream of network communication. In response to detecting the first identifier, the controller is further configured to direct the first communication unit away from the network and back toward the controller through a loopback pathway. The controller is further configured to direct the stream of network communication away from the computer system and to the network.

Diagnosis of a network adapter during network operation

Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Tracking statistics corresponding to data access in a computer system

A computer-implemented method for migrating a buffer used for direct memory access (DMA) may include receiving a request to perform a DMA data transfer between a first partitionable endpoint and a buffer of a first memory in a system having two or more processor chips. Each processor chip may have an associated memory and one or more partitionable endpoints. The buffer from the first memory may be migrated to a second memory based on whether the first memory is local or remote to the first partitionable endpoint, and based on a DMA data transfer activity level. A memory is local to a partitionable endpoint when the memory and the partitionable endpoint are associated with a same processor chip. The DMA data transfer may then be performed.

Migrating buffer for direct memory access in a computer system

Disclosed aspects relate to memory affinity management in a shared pool of configurable computing resources that utilizes non-uniform memory access (NUMA). An access relationship is monitored between a set of hardware memory components and a set of software assets. A set of memory affinity data is stored. The set of memory affinity data indicates the access relationship between the set of software assets and the set of hardware memory components. Using the set of memory affinity data, a NUMA utilization configuration with respect to the set of software assets is determined. Based on the NUMA utilization configuration, a set of accesses pertaining to the set of software assets and the set of hardware memory components is executed.

Memory affinity management

A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is associated with a hardware thread of a processor of the computer system. The entitlement processor resource percentage for the logical partition is stored in a register of the hardware thread associated with the logical partition. An instruction is received from the logical partition of the computer system and the processor dispatches the instruction based on the entitlement processor resource percentage stored in the register of the hardware thread associated with the logical partition.

Honoring hardware entitlement of a hardware thread

Tracking data transfers in an input/output adapter card system to determine whether the adapter cards are well-placed with respect to the components (for example dynamic random access memories) with which the adapter cards respectively are observed to communicate data. Some embodiments use a heuristic value for each adapter card in the system based on inter node transfers and intra node transfers, which are separately weighted and summed over some predetermined time interval in order to obtain the heuristic value.

Placement of input / output adapter cards in a server

When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.

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Bengaluru, India

Mehulkumar Patel