Lenovo (singapore) Pte. Ltd.

International Business Machines Corporation

Mehul M Shah

Wingcheung Tam

Gary David Cudak

Pravin S Patel

James Joseph Parsonese

Newton P Liu

Raghuswamyreddy Gundam

Douglas R Oliver

Shiva R Dasari

Wen Wei Tang

Nicholas A Ramirez

Timothy M Wiwel

Karthik Kolavasi

Yun Yu Wang

Thomas D Lovett

Bruce Michael Gilbert

He Huang

Wayne Alan Downer

Adam Lee Soderlund

Ryuji Orita

Steven Mark Thurber

William Joseph Armstrong

David R Engebretsen

Paul Daniel Kangas

Curtis Carl Wollbrink

Scott Neil Dunham

Terence K Rodrigues

Kevin Michael McBride

Ronald Ernest Freking

Sudhir Dhawan

Mark Walz Wenning

Robert K Sloan

Mark A Brandyberry

Dustin Patterson

Robert H Bass

Bill Thanh Huynh

Sean P Brogan

Thanh Vu Nguyen

Joshua H Israel

Suresh Lavani

A multi-processor system includes first and second central processing units (CPUs) connected by a processor interconnect, a single baseboard management controller for managing operation of the first and second CPUs, wherein the first and second CPUs are operable as a single unified node, and a single keyboard, video and mouse connection, wherein the single keyboard, video and mouse connection includes a video controller and a USB controller. The multi-processor system may further comprise a multiplexer connected to the video controller and the USB controller, wherein the multiplexer has a selectable PCIe connection to either the first central processing unit or the second central processing unit. Program instructions may be executable by the baseboard management controller to send a selection signal to the multiplexer.

Multiplexer for selectively connecting a single KVM connection to multiple central processing units

A method for automatically switching input/output ('I/O') between partitioned systems based on power usage includes monitoring power usage for each of two or more systems, selecting a system of the two or more systems in response to power usage of the of the system reaching a power usage threshold, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to an electronic display.

Auto switching video by power usage

A method for automatically switching input/output ('I/O') between partitioned systems based on system events includes monitoring a system state for each of two or more systems sharing an electronic display, where each of the two or more systems includes a processor executing an instance of an operating system, selecting a system of the two or more systems sharing the electronic display in response to determining that a change has occurred in the system state of the of the selected system, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to the electronic display.

System and method for auto switching video by system events

A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.

Independent control of power, clock, and/or reset signals to a partitioned node

A baseboard management controller in a multi-processor system may perform operations including: identifying a partitioning mode (partitioned state or unified state) to implement on the multi-processor system having first and second central processing units (CPUs) located on a single motherboard; accessing, in response to the partitioned state, a first partitioned node configuration (P1C) for a first partitioned node (P1) and a second partitioned node configuration (P2C) for a second partitioned node (P2), wherein P1C identifies a first firmware interface level (F1L) and a first operating system to be used by P1, and wherein P2C identifies a second firmware interface level (F2L) and a second operating system to be used by P2; and causing the first CPU to load a first firmware interface having the identified F1L identified in the P1C and causing the second CPU to load a second firmware interface having the F2L identified in the P2C.

Multiple firmware levels in a partitionable multi-processor system

A baseboard management controller in a multi-processor system may perform operations including: causing, during a first time period, the system to operate in a partitioned state with a first partitioned node including a first subset of components of the system and a second partitioned node including a second subset of components of the system, wherein the first and second partitioned nodes are independently operable nodes having their own operating systems, and wherein the first partitioned node boots from a first boot drive that is included in the first subset; causing, during a second time period, the system to operate in a unified state with a single unified node including components from both the first and second subsets of components, wherein the single unified node has its own operating system; and causing the first boot drive to be inaccessible to the second partitioned node and the single unified node.

Making a boot drive for a first partition inaccessible to other partitions in a partitionable system

A system includes a partitionable multi-processor motherboard that has multiple central processing units, wherein the multi-processor motherboard may be configured to operate as a single unified node or configured to operate as multiple independent partitioned nodes. The system further comprises a single power button that is accessible to a user, wherein the single power button generates an output signal while being pressed, and an integrated circuit installed on the motherboard and connected to receive the output signal from the power button, wherein the integrated circuit stores a first button press gesture definition associated with selection of a first partitioned node, a second button press gesture definition associated with selection of a second partitioned node, and a third button press gesture definition associated with sequencing power to the selected one of the first or second partitioned nodes.

Button press gestures on a single power button to power sequence a selected partitioned node

A computer program product includes a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include initiating disabling of a processor interconnect between first and second central processing units in the multi-processor system and initiating boot of the first central processing unit, wherein the first central processing unit operates in a first partitioned node independent of the second central processing unit.

Partitioning a multi-processor system having a single baseboard management controller

Embodiments provide a method and computer program product including program instructions executable by a baseboard management controller in a multi-processor system to perform various operations. The operations include detecting a number of memory modules connected to each of a plurality of central processing units (CPUs) in the multi-processor system during boot, initiating operation of the multi-processor system as a single unified node in response to each of the CPUs being connected to an equal number of memory modules, and initiating partitioning of the multi-processor system into a first partitioned node and a second partitioned node in response to a first set of one or more of the CPUs each being connected to a first number of memory modules and a second set of one or more of the CPUs each being connected to a second number of memory modules that is different than the first number of memory modules.

Partitioning responsive to processors having a disparate number of memory modules

A system includes a CPU including a primary address decode logic module (PADLM) and a plurality of diagnostic registers, wherein the PADLM includes address bus inputs, and an enable input port. The system further includes a data flip-flop having a data input coupled to a master enable signal line, a set input coupled to an interrupt signal line, an output coupled to the enable input port of the PADLM, and a clock input. Still further, the system includes an address decode logic module having a memory address input and an output indicating whether the memory address is within a predetermined address range of the diagnostic registers, wherein the output of the address decode logic module is coupled to the clock input. Memory mapping is enabled in response to receiving an interrupt signal and determining that the memory address is within a predetermined range of memory addresses for diagnostic registers.

Accessing hidden diagnostic registers

A server motherboard diagnosis method, system, and related circuit system. A management module of the server motherboard and peripheral devices managed by the management module are capable of being powered by a server power source and a USB port. In response to the management module and the peripheral devices being powered by the USB port, a power supply line of the server power source is isolated, as by: identifying the peripheral devices, in response to the management module and the peripheral devices being powered by the USB port; for each of the identified peripheral devices, initializing the peripheral device, and then shutting down the power supply of the peripheral device; establishing a communication between the management module and a diagnosis host through the USB port; and executing a command in response to the command being received from the diagnosis host.

Diagnosis for a server motherboard

In a method for ejecting a plurality of hot plug slots sharing a power controller, a processor receives a request to eject a plurality of hot plug slots, wherein the plurality of hot plug slots share a power controller and have at least two adapters present. A processor causes an OS to incrementally eject the at least two adapters, wherein ejecting an adapter comprises the OS stopping at least one driver of the adapter, and the OS generating a request to remove power from a hot plug slot. Responsive to a request by the OS to remove power from a hot plug slot, a processor generates a signal that prevents the OS from recognizing the adapter is present in the hot plug slot. Responsive to all device drivers for the at least two adapters being stopped, a processor causes power to be removed from the plurality of hot plug slots.

Hot removing an I/O module with multiple hot plug slots

Provisioning memory in a memory system for mirroring includes: gathering, by a memory controller, margin data for memory in the memory system, the margin data representing susceptibility for error; identifying, by the memory controller in dependence upon provisioning criteria and the margin data, mirroring candidates within the memory system; and mirroring, by the memory controller, memory of the memory system utilizing the mirroring candidates as a mirrored backup of other memory in the memory system.

Provisioning memory in a memory system for mirroring

A system includes a multi-node chassis including a chassis management module, a plurality of compute nodes, and a physical presence manual actuator for transmitting a physical presence signal to each compute node in response to manual actuation. Each server has a firmware interface, a trusted platform module, and an AND gate. The firmware interface has a general purpose input output pin for providing an enabling signal in response to a user instruction to a firmware interface setup program that communicates with the firmware interface. The AND gate has a first input receiving the enabling signal, a second input receiving the physical presence signal, and an output coupled to the trusted platform module, wherein the AND gate for a selected compute node asserts physical presence to the trusted platform module of the selected compute node in response to receiving both the enabling signal and the physical presence signal.

System with manual actuator for asserting physical presence across multiple compute nodes

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Beaverton, OR, United States of America

Mehul M Shah