Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Other

Mehul D Shroff

Mark Douglas Hall

Douglas Michael Reber

Edward Outlaw Travis, Jr

Frank Kelsey Baker, Jr

Paul Grudowski

Ertugrul Demircan

Xavier Hours

Ruiqi Tian

Philip Grigg

Venkat Kolagunta

Nihaar N Mahatme

Bradley Paul Smith

Dharmesh Jawarani

James Derek Legg

Chad Weintraub

Terry Alan Breeden

Christophe Oger

William F Johnstone

David M Schraub

Donald E Smeltzer

Brian J Fisher

Vikas R Sheth

Peter Abramowitz

Gerald G Benard

Traci L Smith

Sung-Taeg Kang

Brian A Winstead

Jane A Yater

Tab Allen Stephens

Konstantin V Loiko

Stanley Michael Filipiak

Willard E Conley

Erwin J Prinz

Kurt H Junker

Chi-Min Yuan

Jonathan L Cobb

Sanjay Parihar

Kirk J Strozewski

Kevin Dean Lucas

James Edward Vasek

Jinmiao James Shen

Steven G H Anderson

Jin Miao Shen

Robert Boone

Pascal Caunegre

William D Darlington

Zhi-Xiong Jiang

Jason T Porter

Aldric L'Hernault

A packaged integrated circuit includes a photodiode and a memory. The photodiode generates energy when radiation strikes a surface of the photodiode. The memory includes a plurality of non-volatile memory cells and memory control circuitry. The memory control circuitry is configured to perform an operation to change values stored in at least some of the memory cells of the plurality of non-volatile memory cells while being powered by energy generated by the photodiode. An encapsulant at least partially encapsulates the photodiode and the memory, in which the encapsulant blocks radiation from reaching the surface of the photodiode.

Packaged integrated circuit having a photodiode and a resistive memory

An integrated circuit includes a magneto resistive RAM (MRAM) array having a plurality of MRAM cells, and a set of at least one Hall sensor circuit, each of the set including a Hall sensor to detect a magnetic field. The integrated circuit also includes magnetic processing circuitry for receiving at least one indication from the set of at least one Hall sensor circuit. The magnetic processing circuitry including an output to provide an indication of a possible magnetic field threat to the MRAM array based on the at least one indication from the set.

Magnetic attack detection in a magnetic random access memory (MRAM)

A method of making a semiconductor device with an air gap for a terminal of a semiconductor device includes forming a sacrificial sidewall spacer and removing the spacer after the formation of contact structures for the semiconductor device. The air gap is located in portions of the wafer where the sacrificial air gap was removed. Since the contacts are formed prior to the removal of the sacrificial spacers, air gaps can advantageously be formed without electrically conductive contact material undesirably being deposited in locations of the desired air gap.

Post contact air gap formation

A semiconductor device and a method for making the semiconductor device are provided. The method of making the semiconductor device may include patterning a layer for a first conductor and a second conductor, plating patterned portions of the layer to form the first conductor and the second conductor, removing patterned material to form an air gap between the first conductor and the second conductor, applying a self-supporting film on top of the first conductor and the second conductor to enclose the air gap, and reacting the self-supporting film causing the self-supporting film to be substantially non-conductive.

Method of forming inter-level dielectric structures on semiconductor devices

A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.

Semiconductor device with graphene encapsulated metal and method therefor

A multigate transistor is formed on a wafer with a first material and a second material. Portions of the second material are selectively removed from the first material to form an opening in the first material. An epitaxially grown semiconductor material is grown from a seed layer into the opening. A portion of the first material is removed around the epitaxially grown semiconductor material in the opening and a gate material is formed in locations of the removed first material. The epitaxially grown semiconductor material in the opening serves as a channel region for a multigate transistor and the gate material serves as a gate for the multigate transistor.

Multigate transistor

The use of a netlist or other database containing topological information of an electrical circuit comprising a multiplicity of components which are to undergo safe operating area (SOA) checking, permits a relationship between recorded SOA errors to be established. Knowing how such errors may be interdependent can assist designers in deciding which errors should be rectified first. The relationship between the recorded errors relating to two connected components may be modified by a confidence factor based on elapsed time between the occurrence of the two recorded errors.

Safe operating area checking method and apparatus

In some embodiments, a substrate contact is formed by forming a first gate structure and a second gate structure. The first gate structure is formed in a first volume in a first area of the wafer and the second gate structure is formed in a second volume in a second area of the wafer. The gate dielectric is removed from the wafer in a first area of the wafer but remains in the second area. A first sidewall spacer formed for the gate structure and a second sidewall spacer is formed for the second gate structure. In some embodiments, the first gate structure can be utilized as a substrate contact and the second gate structure can be utilized as a gate of a transistor. In other embodiments, the first gate structure and the second gate structure can be removed and a metal gate material can be deposited in opening for forming a substrate contact and a metal gate, respectively. In some embodiments, the first gate structure (or the replacement metal gate structure) can be used as part of a body contact to bias the body of a transistor. In other embodiments, the first gate structure (or replacement metal gate structure) can be used as part of a current terminal contact for the transistor.

Substrate contacts for a transistor

An integrated circuit device includes a first line in a first metal layer of the integrated circuit device, wherein the first line forms at least a portion of an interconnect, a second line in a second metal layer of the integrated circuit device, and a first via that couples the first line to the second line. The integrated circuit device further includes a first stressor disposed at a first area of the interconnect, wherein the first area at least partially overlaps the first via, wherein the first stressor alters an electromigration stress profile for the interconnect by altering a stress at the first area to be less tensile.

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one TSV (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die. The solar cell die is configured to power the circuitry die. The solar cell die includes a transparent contact on a front side of the solar cell die. A back side of the solar cell die is attached to the back side of the circuitry die and makes electrical contact with the metallization layer on the back side of the circuitry die.

Solar cell powered integrated circuit device and method therefor

A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

Applications for nanopillar structures

A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits.

Voltage and current limits for electronic device based on temperature range

A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry.

Semiconductor device with upset event detection and method of making

A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

Fuse/resistor utilizing interconnect and vias and method of making

Growing community of inventors

Austin, TX, United States of America

Mehul D Shroff