Rambus Inc.

Semtech Corporation

Snowbush Inc.

Mehrdad Ramezani

David J Cassan

Marcus Van Ierssel

Christopher D Holdenried

Sang-Wook Paul Park

Kamran Farzan

Kenneth William Martin

Angus William McLaren

Saman Sadr

Tony Pialis

Jonathan E Rogers

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

Deserialized dual-loop clock radio and data recovery circuit

A high speed transmit driver is provided, along with methods to improve driver slew rate, decrease transmit jitter, improve termination accuracy, and decrease sensitivity to supply noise.

High-speed SSR transmit driver

A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a phase difference between the incoming data signal and the feedback clock signal; a dual path filter for receiving the phase detector output signal, the dual path filter including a first path for generating a digital proportional output signal that is proportional to the phase detector output signal and a second path having an integral digital filter for generating a digital integral output signal that is proportional to an integral of the phase detector output signal; and a digitally controlled oscillator for receiving the proportional output signal and the integral output signal as tuning inputs and generating in dependence thereon an output clock signal from which the feedback clock signal is obtained. The circuit can be implemented in a receive path of a serializer/deserializer.

Serializer deserializer circuits

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Toronto, Canada

Mehrdad Ramezani