Sandisk Corporation

Ict International Cmos Technology, Inc.

Mehrdad Mofidi

Raul-Adrian Cernea

Sanjay Mehrotra

Douglas J Lee

Yan Li

Shahzad Khalid

Daniel C Guterman

Jun Li

Prajit Nandi

Dhaval J Brahmbhatt

Raul-Ardian Cernea

An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

Latched address multi-chunk write to EEPROM

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added by a controlled coupling between the adjacent bit lines of the program-inhibited memory storage unit and the still under programming memory storage unit. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Non-volatile memory and method with bit line to bit line coupled compensation

Method for controlling voltage in a non-volatile memory system is provided. The method includes selecting a first input value for a voltage generator system operating in one of a plurality of modes, the first input value controlling a temperature dependent component of a voltage applied to a memory cell; and selecting a second input value for the voltage generator system operating in one of the plurality of modes, the second input value controlling a temperature independent component of the voltage applied to the memory cell. The temperature dependent component of the voltage applied to the memory cell and the temperature independent component of the voltage applied to the memory cell are controlled independently in response to the first input value and the second input value.

Method for controlling voltage in non-volatile memory systems

System for a non-volatile memory system is provided. The non-volatile memory system includes a voltage generator system operating in one of a plurality of modes for generating a voltage applied to a memory cell of the non-volatile memory system. For one of the plurality of modes, a first input value is selected for controlling a temperature dependent component of the voltage and a second input value is selected for controlling a temperature independent component of the voltage. The temperature dependent component of the voltage and the temperature independent component of the voltage are controlled independently in response to the first input value and the second input value.

System for controlling voltage in non-volatile memory systems

When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Non-volatile memory and method with bit line compensation dependent on neighboring operating modes

Non-volatile memory and method with bit line coupled compensation

Concurrent write of multiple chunks of data into multiple subarrays of

An EEPROM device having a plurality of flash EEPROM cells organized in right and left half memory planes each having right and left quad memory blocks is described along with corresponding control circuitry including erase circuitry for concurrently erasing selected addressable data sectors of the EEPROM device. Included in the erase circuitry are a plurality of erase voltage generating circuits, a corresponding plurality of switching circuitry, and switch control circuitry shared by the plurality of switching circuitry for controlling the selectable coupling of erase voltages generated by the erase voltage generating circuits to corresponding data sectors of the EEPROM device. To minimize the die size of an integrated circuit including such an EEPROM device, the switching circuitry is formed adjacent elongated gap regions containing contacts for connecting buried diffusion regions of the plurality of flash EEPROM cells to parallel running metal lines to reduce the effective resistance of the bit lines comprising the buried diffusion regions.

Plane decode/virtual sector architecture

A process for manufacturing a flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

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Fremont, CA, United States of America

Mehrdad Mofidi