Nvidia Corporation

Alvand Technologies, Inc.

Agilent Technologies, Inc.

Integrated Device Technology, Inc.

Rockwell Int'l Corp.

Alvand Technology, Inc.

Mehrdad Heshami

Mansour Keramat

Tao Liu

Edward Wai Yeung Liu

Timothy C Kuo

Syed S Islam

Kevin William Glass

Jorge Pernillo

Kenneth D Poulton

Robert M R Neff

Feng Bao

Douglas J Hogberg

Bo Liang

A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog monitor circuit generates the time constant signal and includes N switches, where each switch is controlled by one of the N bits of the control word, each switch is configured to connect or disconnect one or more capacitors of the monitor capacitor assembly thereby generating a time constant signal that represents the time constant of the RC integrated filter.

Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters

An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.

Effective shield structure for improving substrate isolation of analog circuits from noisy digital circuits on a system-on-chip (SOC)

Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.

Seal ring for reducing noise coupling within a system-on-a-chip (SoC)

A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems

A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference ('EMI') at relatively high data rates while reducing the manufacturing complexities associated with conventional data links. In one embodiment, a radio frequency ('RF') antenna system includes an antenna and an RF radio coupled to the antenna for receiving wireless RF signals. In particular, the RF radio is configured to digitize RF signals at a fixed data rate to form digitized data signals and to apply the digitized data signals at a variable data rate to a high-speed digital link. The variable data rate distributes the signal energy of the digitized data signals over one or more bands of frequencies, thereby beneficially altering an EMI spectral profile describing emissions that develop as the digitized data signals are transported through a channel.

Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications

A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Fabricated cylinder capacitor for a digital-to-analog converter

A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Fabricated U-shaped capacitor for a digital-to-analog converter

A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Fabricated layered capacitor for a digital-to-analog converter

An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

Analog-to-digital converter architecture using a capacitor array structure

A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

CMOS controlled-impedance transmission line driver

The invention relates to a clock signal frequency multiplier circuit. The circuit multiplies the speed of a clock signal of an integrated circuit (IC) by a factor N to generate a times-N clock signal. The circuit first receives a clock signal. Next, the circuit replicates the clock signal into a plurality of N component signals. Each Jth component signal is delayed from the (J-1)th component signal by 1/N cycles, where J equals 1 to N. The (J=1)th component signal is the clock signal. The N component signals are referred to as phase-shifted components. Finally, the circuit logically combines the phase-shifted components into a times-N clock signal.

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Palo Alto, CA, United States of America

Mehrdad Heshami