Xilinx, Inc.

Mehrdad Eslami Dehkordi

Paul D Kundarewich

Sridhar Krishnamurthy

Guenter Stenz

Grigor S Gasparyan

Marvin Tom

Satish B Sivaswamy

Xiaojian Yang

Frank Mueller

Amish Pandya

Chun Zhang

Frederic Revenu

Garik Mkrtchyan

Abhishek Joshi

Xiao Dong

Nicholas A Mezei

Raoul Badaoui

Meghraj Kalase

Karthic P

Srinivasan Dasasathyan

Zhaoxuan Shen

Thomas O Satter

Vishal Tripathi

Wuxi Li

Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

Optimizing use of computer resources in implementing circuit designs through machine learning

Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

Disclosed approaches for processing a circuit design include interrupting processing of a circuit design by an electronic design automation (EDA) tool at a selected phase of processing. The tool serializes EDA state data into serialized state data while processing is interrupted and writes the serialized state data for subsequent restoration of tool state. To resume processing at the point of interruption, the EDA tool can read the serialized state data and deserialize the serialized state data. The EDA tool bypasses one or more phases of processing after reading the serialized state data and thereafter resumes processing of the circuit design.

Serialization in electronic design automation flows

Examples described herein provide a non-transitory computer-readable medium storing instructions, which when executed by one or more processors, cause the one or more processors to perform operations. The operations include: generating, using the one or more processors, a plurality of child processes according to a number of programmable dies of the multi-die device, each of the plurality of child processes corresponding to a respective programmable die of the multi-die device, wherein the plurality of child processes execute on different processors; partitioning a design for the multi-die device into a plurality of portions, each of the portions to be used to configure one of the programmable dies of the multi-die device; transmitting the plurality of portions of the design to the plurality of child processes for placement; and receiving placements from the plurality of child processes.

Multiprocessing flow and massively multi-threaded flow for multi-die devices

Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

Incremental initialization by parent and child placer processes in processing a circuit design

Some examples described herein provide for clock tree generation for a programmable logic device, and more specifically, for clock tree generation in conjunction or simultaneous with placement of logic for a programmable logic device. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to: generate clock trees in conjunction with placing logic for an application to be implemented in a programmable logic region of a programmable logic device; generate data routes between the placed logic; and generate a physical implementation of the application based on the placed logic, the clock trees, and the data routes. The physical implementation is capable of being loaded on the programmable logic region of the programmable logic device.

Clock tree routing in programmable logic device

The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.

Generating clock trees for a circuit design

Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.

Placement and routing of clock signals for a circuit design

Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.

Growing community of inventors

Los Gatos, CA, United States of America

Mehrdad Eslami Dehkordi