Marvell Asia Pte., Ltd.

Cavium, Inc.

Mehran Nekuii

Hong Jik Kim

Frank Henry Worrell

Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames. In an exemplary embodiment, a method includes decoding instructions included in a job description list, and configuring one or more processing functions of a transceiver to process a radio signal associated with a selected sector based on the decoded instructions. The configuration of the processing functions is synchronized according to time control instructions included in the job description list.

Methods and apparatus for configuring a front end to process multiple sectors with multiple radio frequency frames

A new approach is proposed to support efficient convolution for deep learning by vectorizing multi-dimensional input data for multi-dimensional fast Fourier transform (FFT) and direct memory access (DMA) for data transfer. Specifically, a deep learning processor (DLP) includes a plurality of tensor engines each configured to perform convolution operations by applying one or more kernels on multi-dimensional input data for pattern recognition and classification based on a neural network, wherein each tensor engine includes, among other components, one or more vector processing engines each configured to vectorize the multi-dimensional input data at each layer of the neural network to generate a plurality of vectors and to perform multi-dimensional FFT on the generated vectors and/or the kernels to create output for the convolution operations. Each tensor engine further includes a data engine configured to prefetch the multi-dimensional data and/or the kernels to both on-chip and external memories via DMA.

Systems and methods for vectorized FFT for multidimensional convolution operations

Systems and methods for vectorized FFT for multi-dimensional convolution operations

Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture. In one aspect, an apparatus includes a radix-2 (R2) single delay feedback (SDF) stage that generates a radix-2 output and a radix-3 (R3) SDF stage that generates a radix-3 output. The apparatus also includes one or more radix-2 squared (R2^2) SDF stages that generate a radix-4 output. The apparatus further includes a controller that configures a sequence of radix stages selected from the R2, R3, and R2^2 stages based on an FFT point size to form an FFT engine. The FFT engine receives input samples at a first stage of the sequence and generate an FFT output result that is output from a last stage of the sequence. The sequence includes no more than one R3 stage.

Methods and apparatus for providing an FFT engine using a reconfigurable single delay feedback architecture

A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. The process, in one aspect, is able to receive a data stream formatted with soft information from a communication network such as a wireless network. After identifying a set of bits representing a first logic value from a portion of the data stream in accordance with a predefined soft encoding scheme, the set of bits is compressed into a compressed set of bits. The compressed set of bits which represents the first logic value is subsequently stored in a local memory.

Method and apparatus for improving data integrity using compressed soft information

Method and apparatus for quantizing soft information using linear quantization

A process capable of employing compression and decompression mechanism to receive and decode soft information is disclosed. Upon receiving a set of signals representing a logic value from a transmitter via a physical communication channel, the set of signals is demodulated in accordance with a soft decoding scheme and subsequently, a Log Likelihood Ratio ('LLR') value representing the logic value is generated. After generating a quantized LLR value in response to the LLR value via a non-linear LLR quantizer, the quantized LLR value representing the compressed logic value is stored in a local storage.

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San Jose, CA, United States of America

Mehran Nekuii