Hrl Laboratories, LLC

Telefonaktiebolaget Lm Ericsson (publ)

Tialinx, Inc.

Mehran Mokhtari

James Chingwei Li

Rajesh D Rajavel

David H Chow

Marko Sokolich

Mary Y Chen

Steven S Bui

Anders Djupsj&ouml;backa

Peeter Ellervee

Farrokh Mohamadi

Joseph F Jensen

Hossein H Izadpanah

Mohsen Zolghadri

Lars Thyl&eacute;n

Sverker H&aring;rd

Urban Westergren

A plurality of power amplifiers are integrated into a semiconductor substrate and coupled to a corresponding first plurality of antennas on an adjacent first microwave substrate. A second microwave substrate carries a second plurality of antennas coupled to a combining network. The second microwave substrate is separated from the first microwave substrate to allow a free space combination of RF energy propagated by the first plurality of antennas.

Wafer scale spatial power combiner

In one embodiment, an opto-electronic analog-to-digital converter is provided that includes: an optical comb generator for generating a plurality of optical comb lines; a tunable optical filter adapted to select a portion of the optical comb lines responsive to an analog signal being digitized; a diffractive media for spatially mapping the selected optical comb lines and an array of photodetectors for detecting the spatially mapped optical comb lines.

Opto-electronic analog-to-digital converter

Described is circuitry for improving the acquisition/locking time of phase-locked loops (PLL). The circuitry includes a node for tapping voltage from a PLL, with an analog-to-digital converter (ADC) to convert the voltage to a digital signal. A memory module stores the digital signal. A digital-to-analog converter (DAC) converts the digital signal to an analog output. A comparator/threshold detector is included to compare the voltage from the node to the analog signal from the DAC. Based on the comparison, the comparator/threshold detector provides a signal to the memory module to cause the memory module to update its stored digital signal. Upon power-up, the saved voltage is forced into the PLL to force the PLL nodes to the saved values as an initial condition, thereby decreasing acquisition time in the phased locked loop.

Circuitry and algorithm for improvement of acquisition time in phase-locked loops

A method and apparatus for conditioning a wireless data communication path for the transmission of a signal wave are presented. The apparatus comprises a conditioning wave transmitter positioned to transmit a conditioning wave along at least a portion of the wireless data communication path. The conditioning wave forms a conditioning envelope about the data communication path. The wavelength of the conditioning wave is selected to remove undesirable particles from the wireless data communication path. As a result, the wireless data communication path is conditioned to provide for improved data communication. The conditioning wave may be transmitted co-, counter-, or bi-directionally with respect to the signal wave, and may form a second data channel.

Method and apparatus for conditioning a transmission path for free-space optical wireless data communications

An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.

Electronic device with reduced interface charge between epitaxially grown layers and a method for making the same

An analog to digital converter comprises a plurality of comparators, each comparator for comparing an input electrical signal with a respective, pre-selected reference electrical signal, an encoder coupled to the comparators to receive a detection signal from each comparator indicative of the input signal, and a plurality of reference circuits, each reference circuit coupled to a respective one of the plurality of comparators to supply the respective reference electrical signal to the respective comparator.

Reprogrammable distributed reference ladder for analog-to-digital converters

An opto-electronic A/D converter includes a tunable laser for wavelength modulating a narrowband coherent electromagnetic beam by the amplitude of the analog signal. A grating transforms the wavelength modulated beam into a corresponding angularly modulated beam. A set of kinoforms diffract the angularly modulated beam into a bundle of diffracted beams. Detectors determine the digital signal by repeatedly sampling the spatial power distribution of the diffracted beams.

Optical system and method for performing analog to digital conversion

The present invention relates to the encoding and decoding. respectively, of serial data, using block codes. Encoding of a serial bit stream of input data in groups of N bits, so-called words (O), to serial output data in groups of 2N bits, so-called code words (KO), is preferably carried out by a logic circuit in a manner such that N of the 2N bits in the code words (KO) are comprised of the N bits input data, unchanged or inverted, and remaining bits in the code words (KO) are determined so that, seen statistically, the code words (KO) will include approximately as many zeros as ones, such that each code word (KO) will be unique for each word (O), and such that at least one of the code words (KO) will remain unique even in bit stream shifting processes. Decoding includes further encoding in a similar logic circuit and comparison of the incoming code words with the code words encoded in the logic circuit, in a predetermined manner.

Method and apparatus for encoding/decoding N-bit data into 2N-bit codewords

The present invention relates to the encoding and decoding respectively of serial data, using block codes. Encoding of a serial bit stream of input data in groups of N bits, so-called words (O), to serial output data in groups of 2N bits, so-called code words (KO), is preferably carried out by a logic circuit in a manner such that N of the 2N bits in the code words (KO) are comprised of the N bits input data, unchanged or inverted, and remaining bits in the code words (KO) are determined so that, seen statistically, the code words (KO) will include approximately as many zeros as ones, such that each code word (KO) will be unique for each word (O), and such that at least one of the code words (KO) will remain unique even in bit stream shifting processes. Decoding includes further encoding in a similar logic circuit and comparison of the incoming code words with the code words encoded in the logic circuit, in a predetermined manner.

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Thousand Oaks, CA, United States of America

Mehran Mokhtari