Qualcomm Incorporated

Cadence Design Systems, Inc.

Mehran Mohammadi Izad

Masoud Moslehi Bajestan

Mohammad Farazian

Stefanos Sidiropoulos

Steven Elliott Mikes

Aida Varzaghani

Dimitrios Loizos

Manohar Bhavsar Nagaraju

Paul Lee

Sudipta Sarkar

Bardia Bozorgzadeh

Embodiments included herein are directed towards a fractional feedback divider circuit and associated method. The circuit may include a programmable feedback divider including a plurality of flip-flops arranged in series. The programmable feedback divider may be configured to receive an input clock signal and a reset signal comprising at least one pulse and to generate a divided clock. The circuit may include reset logic configured to receive an input from the programmable feedback divider and to generate a reset signal. The circuit may include a first D flip-flop configured to receive the reset signal and to generate an output and a second D flip-flop configured to receive the output from the first D flip-flop and to generate a second output. The circuit may further include a multiplexer configured to receive the second output and to generate an output clock signal.

Programmable fractional ripple divider

An IC chip can include a buffer and correction module that receives a set of multiphase clock signals at a given frequency, the buffer and correction module can include a differential skew detector that detects a skew between signals of the set of multiphase clock signals. The skew detector can include a set of SR latches. Differential clock signals of the set of multiphase clock signals are input into each SR latch, and the differential clock signals of the set of multiphase clock signals are set to be 180 degrees out of phase. A voltage difference between a DC component of a first output signal and a DC component of a second output signal of a respective SR latch in the set of SR latches varies as a function of the skew between the differential clock signals of the set of multiphase clock signals.

Differential clock skew detector

The present disclosure describes aspects of a switchable inductor network for wideband circuits. In some aspects, the switchable inductor network provides selectable inductance. The switchable inductor network includes a first coil and a second coil that includes a first inductive segment and a second inductive segment. Connection points of the second coil connect the second coil across a portion of the first coil. The switchable inductor network also includes a switch connected between the first inductive segment and the second inductive segment of the second coil. The switch is configured to change the selectable inductance of the switchable inductor network by selectively coupling the first inductive segment to the second inductive segment of the second coil in response to a control signal.

Switchable inductor network for wideband circuits

The present disclosure describes aspects of degeneration for a wideband voltage-controlled oscillator (VCO) circuit. In some aspects, the VCO circuit includes a degeneration network that includes a first inductor, a second inductor, and a capacitor. The degeneration network is connected between the a supply voltage and ground, with the capacitor connected across the differential VCO, between the sources of cross-coupled PMOS transistors and the sources of cross-coupled NMOS transistors. Control circuitry selects an inductance value of a switched inductance network to select a frequency band in which the VCO circuit operates. The control circuitry also sets a switched capacitor bank and a variable capacitor bank to tune the VCO circuit to an operating frequency within the selected frequency band. The control circuitry further tunes the degeneration network to degenerate the VCO circuit to reduce phase noise in an output signal of the VCO circuit.

Degeneration for a wideband voltage-controlled oscillator

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San Diego, CA, United States of America

Mehran Mohammadi Izad