S3 Incorporated, Inc.

Mehran Amerian

Kenneth D Wagner

Srinivasan R Iyengar

Max Hamidi

An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.

Edge-triggered scan flip-flop and one-pass scan synthesis methodology

An integrated circuit includes a first circuit module for generating a plurality of digital signals and a second circuit module for receiving the digital signals. A multiple input signature module receives the digital signals that are received by the second circuit module. The signature module generates and stores a signature value which is indicative of data values of the digital signals over a plurality of cycles. The signature module operates in response to control circuitry, which is responsive to a test signal, to cause the values indicative of the digital signals to be stored to the multiple input signature module, each time that valid signal values are received by the second circuit module. The multiple input signature module may be used for diagnostics by capturing data at a single, predetermined cycle. The module may be initialized to a predetermined value to ensure the signature value or, the single value captured, accurately reflects the data value of the digital signals. The control circuitry is further responsive to a signature data signal for causing data stored in the multiple input signature module to be provided on at least a first output pin of the integrated circuit. The integrated circuit includes scan circuitry and the signature data signal causes the multiple input signature module to form a portion of the scan circuitry.

Multiple input signature testing & diagnosis for embedded blocks in

The improved pin system enables a single, shared pin of a semiconductor device to have multiple functions that include: receiving data that determines the operating mode of the semiconductor device and also receiving data unrelated to the operating mode of the semiconductor device. The improved pin system comprises the single, shared pin coupled to a data latch. The data latch is configured to store operating mode data from the single, shared pin. This operating mode data preferably corresponds to a particular operating mode such as a functional mode or a test mode. Preferably, in response to the operating mode data stored in the data latch, the semiconductor device operates in either the functional mode or the test mode. As long as the data latch stores the operating mode data, this shared, single pin is capable of receiving data unrelated to the operating mode of the semiconductor device without changing the current operating mode of the semiconductor device.

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Campbell, CA, United States of America

Mehran Amerian