Maxtor Corporation

Lsi Corporation

Microsemi Semiconductor Ulc

Quantum Corporation

Mehran Aliahmad

Russell W Brown

Kristopher Kshonze

Ivan Chan

Bruce A Leshay

Mohammad Shafiul Mobin

Matthew Tota

Gregory Scott Winn

Foad Arfaei Malekzadeh

Nasser Ghassemi

Russ Brown

Substrates configured to route electrical signals may include a first dielectric material and an electrically conductive material located on a first side of the first dielectric material. A second dielectric material may be located on a second, opposite side of the first dielectric material. A series of voids may be defined by the second dielectric material extending from the first dielectric material at least partially through the second dielectric material. Footprints of at least some of the voids of the series of voids may at least partially laterally overlap with the electrically conductive material.

Techniques for routing electrical signals through electrical components and related methods

A method for reducing the jitter introduced into a digital signal by a non-linear processing element involves applying an input word representing the digital signal to a first signal path comprising a first non-linear processing element, and a complementary version of the input word to a second signal path comprising a second non-linear processing element. A common mode dither signal is injected into each signal path upstream of the non-linear processing elements. The outputs of the non-linear processing elements are combined to produce a common output with the common mode dither signal removed.

Noise reduction in non-linear signal processing

A signal generator circuit for reducing power consumption of out-of-band message communications between a first device including the signal generator circuit and a second device coupled to the first device comprises a switching circuit and a controller coupled to the switching circuit. The controller is operative to receive a reference clock signal and at least a first control signal indicative of a request for the first device to send a message to the second device when the first device is in a first mode of operation. The controller generates an output control signal and an output data signal. The output control signal is operative as a function of the first control signal to selectively power up the switching circuit and a transmitter driver during the first mode. The output data signal includes the message supplied to the transmitter driver for transmission to the second device during the first mode.

Methods and apparatus for low power out-of-band communications

Embodiments of the invention include an integrated circuit including a line driver. The integrated circuit includes a voltage mode driver comprising complementary first and second input voltage drivers, a programmable resistor network and a current mode driver. The programmable resistor network allows the amplitude of the line driver outputs to be controlled based on the particular resistor connections in the programmable resistor network. Also, the differential impedance of the integrated circuit and the common mode impedance of the integrated circuit are based on the resistance values of the resistors in the programmable resistor network.

Programmable amplitude line driver

A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.

Timing skew compensation technique for parallel data channels

A circuit for measuring and compensating for DC offset introduced into a differential signal due to, for example, terminator mismatches and interconnect resistance, is described herein. The circuit includes a plurality of capacitors that store test values of a differential signal, a summer, a comparator, a digital counter, and an analog-to-digital converter. The summer sums signals from the plurality of capacitors and a dc offset correction signal from the analog-to-digital converter. A differential output from the summer is processed by the comparator to generate a binary output signal that is used to recursively modify the value of the dc offset correction signal until the dc offset correction signal stabilizes.

Sampled analog DC offset correction for data bus structures

An apparatus mitigates inter-symbol interference effects on an oscillating signal from which digital data will be obtained at a receive end of a channel. The inter-symbol interference is introduced into the oscillating signal as a result of transmitting the oscillating signal through the transmission channel over a substantial distance from a transmit device to the receive end of the channel. A filter element receives an input signal from the transmit device and outputs a filtered signal within a predetermined frequency band. The filter element has a mechanism for adjusting a gain for a given range of frequencies within the predetermined frequency band. The given range of frequencies corresponds to higher frequencies in the predetermined frequency band. An amplitude determining mechanism determines a peak amplitude of the filtered signal. A boost gain control mechanism controls adjustments to the high frequency gain so that the peak-to-peak amplitude of the filtered signal is maintained within a predetermined amplitude range.

Adaptive inter-symbol interference boost equalization apparatus and method

DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for in another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

Apparatus and method for the correction of DC offset in data bus structures at the receiver

An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.

Method and apparatus for performing clock timing de-skew

A phase difference to duty-cycle circuit converts a phase shifted signal and a reference signal into a single signal having a duty cycle that is a function of the phase difference between the two signals. The single signal may be further converted to a single direct current (DC) value before being transmitted to external measurement circuitry. The external measurement circuitry, by simply measuring the magnitude of the DC signal, can determine the phase difference between the phase shifted signal and the reference signal. In an alternate embodiment, the phase shift in the target bit of a bit pattern is determined based on measurements of the DC voltage value of the shifted target bit pattern, the DC voltage value of first bit pattern comprising a non-shifted bit pattern representing a zero phase shift of the target bit, and a DC voltage value of a bit pattern comprising a non-shifted bit pattern representing a 100% phase shift of the target bit.

High-resolution measurement of phase shifts in high frequency phase modulators

DC offset introduced into a differential signal is compensated for by DC offset correction circuitry. The DC offset correction circuitry receives a known training pattern of alternating logic high and logic low levels (i.e., 10101010 etc.). In one embodiment, the received signal is integrated and the result compared to a predetermined reference level. The result of the comparison is used to adjust a DC offset correction value that is added to the received signal. This process is iteratively performed until successive results of the comparison indicate that the DC offset has been compensated for. In another embodiment, the duty-cycle of the received signal is calculated. The result of the duty-cycle calculation is used to iteratively adjust the DC offset correction value.

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Ottawa, Canada

Mehran Aliahmad