Applied Micro Circuits Corporation

Mehmet Mustafa Eker

Viet Linh Do

Simon Pang

Joseph James Balardeta

Wei Fu

Thomas Clark Bryan

Hongming An

Philip Michael Clovis

Harry Huy Dang

Allen Carl Merrill

Sudhaker Reddy Anumula

Michael Hellmer

Wei Li

Paul Edward Vanderbilt

A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired.

Frequency reacquisition in a clock and data recovery device

Adaptive multi-band frequency calibration is provided for a phase-locked loop (PLL). A voltage controller oscillator (VCO) is initially selected nominally associated with first synthesized signal frequency, where the VCO is selected from a plurality of n VCOs, and each VCO is tunable across a band of synthesized signal frequencies. A lock detector compares a nominal first synthesized signal frequency to a reference signal frequency. In response to sensing a difference between the nominal first synthesizer and reference signal frequencies, an out-of-lock condition is asserted and a VCO is reselected from the plurality of n VCOs. A mid-point control voltage is supplied to a control voltage input of the reselected VCO. A difference is measured between a mid-point synthesized signal frequency and the reference signal frequency. If the difference is less than a first threshold, the reselected VCO is assigned to generate the first synthesized signal frequency.

Adaptive phase-locked loop (PLL) multi-band calibration

A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range.

Frequency lock stability in device using overlapping VCO bands

A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

Auto frequency acquisition maintenance in a clock and data recovery device

A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.

Frequency hold mechanism in a clock and data recovery device

A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref1), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref1/n, where n is an integer &#x2267;1. The count for each sampling frequency is compared to the count for Fref1 (n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref1, and the coarse clock frequency is set to Fc1=Fref1/(x&#x2212;1).

Automatic clock frequency acquisition

A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rate&#x2014;to detect if the clock signal is incorrectly locked to the first rate.

False frequency lock detector

A system and method are provided for automatically acquiring a serial data stream clock. The method receives a serial data stream with an unknown clock frequency and coarsely determines the clock frequency. The frequency is coarsely determined by (initially) selecting a high frequency first reference clock (Fref), and counting the number of data transitions in a first time segment of the serial data stream at a plurality of sample frequencies equal to Fref/n, where n is an integer&#x2267;1. The count for each sampling frequency is compared to the count for Fref(n=1). Next, the highest sampling frequency (n=x) is determined, which has a lower count than Fref, and the coarse clock frequency is set to Fc=Fref/(x&#x2212;1).

System and method for automatic clock frequency acquisition

A wide dynamic range charge pump is provided for use in a phase-locked loop (PLL) circuit. The charge pump includes a first, second, and third set of current sources. The charge pump further includes a first capacitor having an input connected to the first set. A first operational amplifier (op amp) has an input connected to the first set output, and an output connected to the second set output and to a voltage controlled oscillator (VCO) input. A first resistor has a first end connected to the first op amp output and a second end connected to the third set. A second capacitor has an input connected to the first resistor second end, and an output connected to the second reference voltage.

Wide dynamic range charge pump

A voltage-controlled oscillator ('VCO') structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.

Dual voltage-controlled oscillator structure with powder-down feature

A CMOS field effect transistor (FET) is provided with predetermined temperature characteristics. More particularly, the relationship between the channel length, gate width, gate-to-source voltage, and drain current is exploited to create an FET that has relatively constant drain current across a relatively wide range of frequencies. Alternately, the above-mentioned relationship is exploited to create a drain current with a predetermined temperature coefficient across a wide temperature range.

Temperature stable CMOS device

A biasing circuit for producing a bias current which is supply-independent and temperature-stable includes a first voltage generating circuit which produces a first voltage V at an output; a second voltage generating circuit which produces a second voltage V different from the first voltage V at an output; a differential amplifier circuit having inputs coupled to the outputs of the first and the second voltage generating circuits and producing a reference voltage V based on a difference between the first voltage V and the second voltage V ; and a current generating circuit which produces a bias current I from the reference voltage V .

Methods and apparatus for generating a supply-independent and temperature-stable bias current

A system and method have been provided for selectably equalizing an input signal to an integrated circuit (IC), to compensate for degradation in the transmission process. The selectable equalization circuit includes parallel equalizing and non-equalizing sections. When the equalizing section is engaged a resonant element modifies the circuit impedance to add a zero to the circuit transfer function. When the non-equalizing function is engaged, the equalizing section is disengaged without degrading gate capacitance, and the input signals are processed without a zero in the transfer function.

Selectable equalization system and method

A driver circuit which has a reduced or eliminated crowbar current includes a P-channel type transistor having a source coupled to a reference voltage; an N-channel type transistor having a source coupled to ground and a drain coupled to a drain of the P-channel type transistor; first logic gate circuitry (e.g., a NOR gate) having an input coupled to a reference clock signal and an output coupled to a gate of the P-channel type transistor; and second logic gate circuitry (e.g., a NAND gate) having an input coupled to the reference clock signal and an output coupled to a gate of the N-channel type transistor. The first logic gate circuitry is designed to have a first input voltage threshold value (e.g., &frac14; V ) that is different from a second input voltage threshold value (e.g., &frac34; V ) of the second logic gate circuitry. Thus, the output from the first logic gate circuitry provides off-to-on transitions which precede off-to-on transitions provided from the output of the second logic gate circuitry and on-to-off transitions which succeed on-to-off transitions provided by the second clock input signal.

Methods and apparatus for reducing the crowbar current in a driver circuit

A configurable PLL architecture having multiple detection elements. The configurable PLL circuit includes a first detector for providing a first differential signal, a second detector for providing a second differential signal, a third detector for providing a third differential signal, and a selection circuit for enabling at least one of the first, second and third detectors. The PLL circuit also includes a multiplexer for receiving at least one differential signal from a corresponding enabled detector, and for providing a multiplexed differential signal output. In operation, an operating mode is selected, and one or more detectors are enabled for operation with one or more input reference signals. The outputs of the enabled detectors is received by the multiplexer to complete the operation of the selected operating mode.

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Santee, CA, United States of America

Mehmet Mustafa Eker