Globalfoundries Inc.

Mehdi Z Sadi

Luke G England

Sukeshwar Kannan

At least one method, apparatus and system disclosed involves performing a dynamic voltage compensation in an integrated circuit. A first voltage on a first portion of an integrated circuit is received. A second voltage on a second portion of the integrated circuit is monitored. A determination is made as to whether the second voltage fell below the first voltage by a predetermined margin. A feedback adjustment of the of the second voltage is performed in response to a determination that the second voltage fell below the first voltage by the predetermined margin; the feedback adjustment comprises performing a step up of the second voltage.

Method, apparatus and system for voltage compensation in a semiconductor wafer

A latency compensation circuit and method. A three dimensional (3D) package is disclosed having a latency compensation circuit to address timing delays introduced by a through silicon via (TSV), including: an input for receiving a reference data signal from a redundant TSV and for receiving a local clock signal; a timing slack sensor that outputs a digital value reflecting a delay between a clock pulse of the local clock signal and the reference data signal; a look-up table that converts the digital value into a set of control bits; and an adjustable delay line that adjusts the local clock signal based on the set of control bits.

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Malta, NY, United States of America

Mehdi Z Sadi