Texas Instruments Corporation

Mehdi-Laurent Akkar

Narendar M Shankar

Aymeric S Vial

Gregory Remy Philippe Conti

Steven C Goss

Gregory R Conti

Steven Charles Goss

Olivier Schuepbach

Aymeric Stéphane Vial

A secure demand paging system () includes a processor () operable for executing instructions, an internal memory () for a first page in a first virtual machine context, an external memory () for a second page in a second virtual machine context, and a security circuit () coupled to the processor () and to the internal memory () for maintaining the first page secure in the internal memory (). The processor () is operable to execute sets of instructions representing: a central controller (), an abort handler () coupled to supply to the central controller () at least one signal representing a page fault by an instruction in the processor (), a scavenger () responsive to the central controller () and operable to identify the first page as a page to free, a virtual machine context switcher () responsive to the central controller () to change from the first virtual machine context to the second virtual machine context; and a swapper manager () operable to swap in the second page from the external memory () with decryption and integrity check, to the internal memory () in place of the first page.

Methods, apparatus, and systems for secure demand paging and paging operations for processor devices

A secure demand paging system including a secure internal memory, an external non-volatile memory having encrypted and integrity-protected code pages, an external volatile memory for swap pages and a processor coupled to said secure internal memory and to said external non-volatile memory and operable to decrypt and verify the integrity of the code pages thereby to transfer code pages to said secure internal memory directly from said external non-volatile memory bypassing said external volatile memory in respect of the code pages, and to swap out and swap in the swap pages between secure internal memory and said external volatile memory bypassing said external non-volatile memory in respect of the swap pages for said external volatile memory.

Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A secure demand paging system includes a processor operable for executing instructions, an internal memory for a first page in a first virtual machine context, an external memory for a second page in a second virtual machine context, and a security circuit coupled to the processor and to the internal memory for maintaining the first page secure in the internal memory. The processor is operable to execute sets of instructions representing: a central controller, an abort handler coupled to supply to the central controller at least one signal representing a page fault by an instruction in the processor, a scavenger responsive to the central controller and operable to identify the first page as a page to free, a virtual machine context switcher responsive to the central controller to change from the first virtual machine context to the second virtual machine context; and a swapper manager operable to swap in the second page from the external memory with decryption and integrity check, to the internal memory in place of the first page.

A system is provided that includes a processor and a random access memory (RAM) coupled to the processor. The RAM is divided into public RAM and secure RAM. The system also includes a system memory coupled to the processor, wherein the system memory stores RAM resize instructions that, when executed, enable the public RAM and the secure RAM to be dynamically resized. The system memory may also store save/restore secure RAM instructions that, when executed, perform a save operation that saves the secure RAM to non-volatile memory and a restore operation that restores the secure RAM from the non-volatile memory. The system memory may also store arbitration instructions that, when executed, enable a cryptographic hardware accelerator (HWA) to be shared by a secure application and a public application.

Methods and systems involving secure RAM

A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.

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Paris, France

Mehdi-Laurent Akkar