Cardiac Pacemakers, Inc.

The Boeing Company

Mehdi Katoozi

Kenneth Frederick Cowan

Scott R Vanderlinde

Joseph E Bange

Prashant Brijmohansing Rawat

Earle Timothy Roberts

Mark Rutzer

Ken Cowan

Allan Thomas Koshiol

Alfio Zanchi

Thomas J Harris

Sylvia Quiles

Thomas M Bocek

George D Jelatis

Krishna Sridharan

George S LaRue

George Sterling La Rue

Tom Bocek

An analog-to-digital converter (ADC) includes at least first thru third ADC slices configured to sample input signal and transmit first thru third digitally converted values thereof, at least one reference ADC slice configured to sample input signal and transmit a digitally converted reference value, first thru third and reference registers coupled to first thru third and reference ADC slices, respectively, a delay register having an input and output, and configured to produce a sample time adjustment signal, where the sample time adjustment signal facilitates adjustment of a phase of a next time sampling of the input signal by the second ADC slice, and a plurality of computational circuit elements coupled to the input, output, and the registers, and configured to determine values of an error, an approximate time derivative of the input signal estimated from the third, second and first sampled time point, and the sample time adjustment signal.

Radiation-hardened interleaved analog-to-digital converter circuits and methods of calibrating the same

An apparatus comprises a transceiver configured to communicate wirelessly with an IMD and a processor communicatively coupled to the transceiver. The processor is configured to detect an error in a data unit received from the IMD, transmit a series of synchronization signals during an uninterrupted communication sequence, and receive, for each synchronization signal, a new data unit and the number of requested duplicate data units from the IMD. Each synchronization signal includes an echo code, wherein the echo code corresponds to a request for a number of duplicate data units to be sent in response to detecting the error in the data unit received during said uninterrupted communication sequence. The number of duplicate data units corresponds to a value of the echo code, and a duplicate data unit corresponds to a data unit previously transmitted by the IMD during said uninterrupted communication sequence.

On-demand retransmission of data with an implantable medical device

A telemetry system for data transmission between an implantable medical device and an external system includes a plurality of channels each representing a frequency band within a predetermined frequency range. The data transmission is performed using at least one active channel at any instant. Channel hopping is performed upon detecting an interruption of communication, such that a scan is performed through an array of channels selected from the plurality of channels. If a data frame is not successfully transmitted, it is repeatedly re-transmitted using the current and/or the next active channels until its transmission becomes successful.

Implantable medical device telemetry with hop-on-error frequency hopping

A method, apparatus, and system of encryption, including embedding reconfiguration information within a ciphertext block destined for a decryptor. The decryptor identifies the reconfiguration information, extracts such information, and uses it to alter a pre-cipher, which is used for decryption. The encryptor alters its pre-cipher synchronously with the decryptor.

Symmetric key encryption system with synchronously updating expanded key

The selection of one communication channel from a plurality of available channels is determined by a state machine. In an automatic selection mode, a first telemetry system has priority over other telemetry systems. A communication session is in progress based on session initiation and termination triggers. An override function allows manual selection of a telemetry system.

Telemetry switchover state machine with firmware priority control

This document discloses, among other things, a telemetry system for requesting and receiving redundant data. A synchronization frame transmitted by an external device includes an echo code. The implantable device responds to the synchronization frame by sending real time data and echo data selected as a function of the echo code.

A control for a pulse width modulated power supply. The control (14) uses a digital pulse width modulator (48, 48') to produce set and reset signals that determine the duration of control pulses supplied to the pulse width modulated power supply (12). In one embodiment, a plurality of analog-to-digital converters (50, 51, 53) convert analog signals indicative of different parameters monitored on the pulse width modulated power supply to digital values. Differences between the digital values and corresponding predefined desired reference values are determined, combined, and the result is input to a digital comparator (72) of the digital pulse width modulator. The digital comparator produces a reset signal when the combined differences equal a count of clock pulses accumulated on a counter (76). A second digital comparator compares the count to a predefined count and produces a set signal when the two digital values are equal. The set and reset signals are applied to a flip-flop (88) to produce the control pulses, and the set signal resets the counter to initiate the next count cycle. In a silicon CMOS embodiment having a limited switching frequency capability, the required resolution is achieved by using a vernier (94) to incrementally delay the reset signal based upon the least significant bits of the difference signal.

Digital pulse width modulator for power supply control

A built-in self-test system and method for use in testing an integrated circuit. An integrated circuit (200) includes a self-test generator (210) that produces pseudo-random test vectors, each having fewer bits than a normal input signal applied to the integrated circuit. The normal signal comprises data and parity bits that are applied to a plurality of error detection and correction (EDAC) circuits (50) on the integrated circuit. Selected bits of the pseudo-random test vectors generated by the self-test generator are fanned out to provide the total number of bits of the data and parity signals, and a test signature is produced after a full set of test vectors have been processed by the EDAC. A signature analyzer (222) compares the test signature with a predetermined expected signature to determine if a fault has occurred in one of the EDACs in the integrated circuit. The self test can be made upon demand, or alternatively, can be run pseudo-concurrently with the normal mode, using cycle stealing.

Built-in self-test system and method for self test of an integrated

A system for performing a self test on a circuit without interrupting its normal function. Several embodiments of a self-test system (10, 60, 80, 100, 120) are disclosed, each of which include a test generator (22) that generates a test signal selectively applied to a circuit under test (CUT) (12, 122). The CUT produces an output signal that is analyzed to determine whether the circuit is operating properly. In several of the embodiments, a signature analyzer (44) compares the signature of the output signal to a predetermined expected signature after a sequence of test vectors have been performed on the CUT. In a fault-tolerant embodiment of the self-test system (100), a plurality of CUTs are evaluated in respect to the output signal produced thereby, both when operating to process a normal input signal and, when processing a test signal. A voter (108) selects an output signal for use by a primary signal utilization device (42) from among the output signals of the redundant CUTs and thus determines whether one of the redundant circuits has failed to operate properly. In each embodiment, the self test can occur either during multiple system clock cycles when the circuit is available, or during a portion of each system clock cycle in which the circuit under test is not required to perform its normal function. In another embodiment involving a first circuit portion (124) that produces an intermediate data state that must be held between successive clock cycles for use by a second circuit portion (126), a latch (130) is used to bypass a latch (128) within the circuit under test, so that both portions of the circuit are evaluated without disrupting operation of the signal utilization device.

Growing community of inventors

Issaquah, WA, United States of America

Mehdi Katoozi