Infinera Corporation

Mehdi Karimi

Sandy Thomson

Yuejian Wu

Scott G Pringle

Han Henry Sun

Scott Pringle

William Isaac

Syed Muhammad Bilal

Christopher Fludger

Systems and methods for performing impairment compensation in point-to-multi-point communication systems are described. In a data snapshot mode, a hub node can send instructions to each communication node connected to the hub node to send a data snapshot of data being received and processed by the communication nodes at a particular time. In a trench line mode, a hub node sends instructions to each communication node to send trench line data back to the hub node. The hub node uses the data snapshot or trench line data to determine how to tune filter coefficients in the hub node to perform impairment compensation and improve performance of the communication system.

Transmission impairment compensation in point-to-multipoint communication systems

A low-density parity-check (LDPC) decoder may comprise a shift register configured to receive LDPC coded data, perform an iteration associated with decoding the LDPC coded data, and provide a result of performing the iteration. The shift register may include a quantity of lanes corresponding to a quantity of data words received by the shift register at a particular clock cycle, a quantity of stages corresponding to a quantity of clock cycles needed to perform the iteration, a quantity of storage elements, associated with storing the data words during the iteration, and a set of check node elements associated with updating the data words during the iteration. The quantity of stages times the quantity of lanes may be greater than the quantity of storage elements by a particular number of storage elements. The particular number of storage elements may be displaced by the set of check node elements.

Efficient storage architecture for low-density parity-check decoding

A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.

Code design and high-throughput decoder architecture for layered decoding of a low-density parity-check code

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Mehdi Karimi