Ncr Corporation

Mehdi H Sani

Donald K Lauffer

Donald G Tipon

Paul M Rostek

The circuits of the present invention convert CMOS logic levels to corresponding ECL logic levels to permit the coupling of CMOS and ECL circuits. One preferred circuit embodiment is comprised of three p-channel transistors and one n-channel transistor. The first p-transistor has its source connected to a reference potential, such as ground, and its drain electrode connected to the source of the second p-transistor. The drain and the gate of the second p-transistor are connected together to an output terminal. The drain of the third p-transistor is connected to the output terminal. The gate and the source of the third p-transistor are connected to the drain of the n-transistor. The source of the n-transistor is connected to a CMOS compatible potential source. The CMOS logic level signal is coupled to the gate of the first p-transistor and the gate of the n-transistor. The output terminal is connected to an ECL compatible potential source via a termination resistor. Two other circuit embodiments are disclosed which provide for non-inverted and inverted outputs.

CMOS to ECL interface circuit

A circuit for assisting transitions of a signal on a bus conductor having a sensing element connected to the bus conductor for determining if the bus conductor is in a first state or a second state, an assisting element for assisting transitions of a signal on the bus conductor between its first state and its second state responsive to electrical clock pulses, and a logic element connected to the sensing element and the assist element for enabling said assist element when the transmission of the mentioned signal is from its first state to its second state during said clock pulses, and for disabling the assisting element when the mentioned signal transition is from its second state to its first state during said clock pulses.

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La Jolla, CA, United States of America

Mehdi H Sani