Cryptography Research, Inc.

Sifive, Inc.

Megan Anneke Wachs

Andrew John Leiserson

Michael Alexander Hamburg

Mark Evan Marson

Ambuj Kumar

Benjamin Che-Ming Jun

Wesley Waylon Terpstra

Henry Cook

Hai Lan

Ralf M Schmitt

Minghui Han

Joseph Inkenbrandt

A container corresponding to executable code may be received. In response receiving the container, an assertion value may be stored in an assertion register. A final canary value may be generated based on a cycles combining a prior canary value and a mix value. A determination may be made as to whether the final canary value matches with the assertion value stored in the assertion register. In response to determining that the final canary value matches with the assertion value, one or more privilege registers may be programmed to provide access to hardware resources for the container corresponding to the executable user code.

Providing access to a hardware resource based on a canary value

A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.

Masked gate logic for resistance to power analysis

Values and a sequence of operations associated with generating a key may be received. A determination may be made as to whether the sequence of operations associated with the key matches an authorized sequence of operations. The key may be outputted when the received sequence of operations matches the authorized sequence of operations and the key may not be outputted when the received sequence of operations does not match the authorized sequence of operations.

Outputting a key based on an authorized sequence of operations

Systems and methods are disclosed for generation and testing of integrated circuit designs with point-to-point connections between modules. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. For example, type parameterization may be used to generate point-to-point connections in a flexible manner. For example, a point-to-point connection between the source module and the sink module that includes one or more named wires specified by bundle type may be automatically generated based on using the bundle type as a type parameterization input. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Point-to-point module connection interface for integrated circuit generation

A first and second set of simulation information of a circuit design may be received. Energy consumption values associated with signals may be calculated for each of the first and second sets of simulation information of the circuit design. The energy consumption values associated with the transitions of the plurality of signals for each time point of a plurality of time points may be aggregated based on when each of the transitions of the signals occurs for each of the first and second sets of simulation information. Furthermore, a possible Differential Power Analysis (DPA) leak may be identified at one of the time points based on a difference in aggregated energy consumption values between the first and second sets of simulation information.

Energy analysis for differential power analysis resistance

A method and system for a countermeasure to power analysis attacks, where an impedance element is coupled to a power source providing power to a cryptographic module causing a measurable power supply noise, a timing sequence is generated, and the impedance element is decoupled from the power source based on the timing sequence to cause the measurable power supply noise to vary according to the timing sequence.

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San Francisco, CA, United States of America

Megan Anneke Wachs