Energy Conversion Devices, Inc.

Ovonic Imaging Systems, Inc.

Meera Vijan

Vincent D Cannella

Zvi Yaniv

Yair Baron

Gregory L Hansell

John C McGill

Paul N Day

A method of forming a large area electronic element, e.g., a large area integrated microelectronic circuit which has at least one dimension in excess of three inches, by forming a film of photoresist separate from a surface to be etched, and thereafter depositing the film of photoresist on the surface to be etched. The deposited photoresist film is then exposed to actinic radiation and developed, and the exposed, underlying surface may thereafter be etched. The method for depositing the photoresist involves passing a viscous liquid composed of photoresist and solvent under positive pressure through a very thin elongated orifice that extends across and in close proximity to (e.g., 0.01 inch or less), but spaced apart from the surface to be processed to form a very thin flexible continuous film of liquid photoresist composition issuing from the orifice. The surface to be processed is linearly moved past the orifice so as to deposit the issued film of photoresist on the surface, in a thickness no greater than 100 microns, and preferably much less. The wet deposited film is then heated to drive off the solvent thereby reducing the thickness of the photoresist. The method disclosed herein is particularly suitable for processing large area rectangular substrates and continuous flexible substrates used in roll-to-roll processing equipment.

Method of forming a large surface area integrated circuit

Thin film semiconductor devices such as amorphous silicon alloy p-i-n diodes and the like which utilize mesa-like semiconductor structures having vertical sidewalls are formed by a process which eliminates overhangs and neutralizes contaminants on the sidewalls that can result in short circuits or degradation of device performance. Smooth vertical sidewalls free of overhangs and voids are created by: successively depositing the desired semiconductor layers on a substrate, then depositing and patterning a top metal contact mask on the semiconductor layers, followed by removing the unwanted portions of the semiconductor layers by reactive ion etching. The disclosed reactive ion etching provides controlled vertical etching with virtually no lateral etching, thereby providing smooth sidewalls. The top metal contact mask protects the underlying semiconductor layers during the anisotropic etching process, and its edges are precisely aligned with the sidewalls of the underlying semiconductor layers that define the mesa structure when the etching is complete. The top metal contact mask which is formed by conventional deposition and patterning techniques, serves as a connection between the metal electrode which connects semiconductor layers of the mesa structure to the top metallization which is patterned to define desired interconnections. Ion damage and contaminants formed on the sidewalls during etching are removed or neutralized by contacting the sidewalls with a base solution and/or annealing the mesa structure before it is covered with an insulation layer.

Method of forming thin film semiconductor devices

Light influencing displays and more particularly liquid crystal displays are disclosed which have a pair of light transmissive electrode supports which are uniformly spaced apart by a predetermined distance over the entire display area. The electrode supports are spaced apart by spacer means including a plurality of spacers arranged in a predetermined pattern between the electrode supports.

Liquid crystal matrix display having improved spacers and method of

A new and improved thin film field effect transistor has increased operating current and speed. The transistor includes a drain, an insulator, and a source formed in layers and vertically arranged with respect to a substrate and each other. The drain, however, and source layers form a plurality of non-coplanar surfaces with respect to the substrate. The device further includes a deposited semiconductor material overlying the non-coplanar surfaces to form a plurality of current conduction channels between the drain and source. A gate insulator overlies the semiconductor material, and a gate electrode overlies the gate insulator. The devices can also include carrier injection structure including a doped semiconductor material electrically coupled to the drain, the source, and the deposited semiconductor material for increasing the injection of current conduction carriers in the current conduction channels.

High current thin film transistor

A method of making a high performance, small area thin film transistor having a drain region, an insulating layer, and a source region forming a non-coplanar surface with respect to a substrate is disclosed. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting the capacitance between the gate electrode and the source region.

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Troy, MI, United States of America

Meera Vijan