Intel Corporation

Stmicroelectronics S.r.l.

Meenatchi Jagasivamani

Ferdinando Bedeschi

Richard Edward Fackenthal

Enzo M Donze

Ravi Annavajjhala

Patrick Wu

Enzo Michele Donzè

Anthony Ko

Enzo Donze'

Rich E Fackenthal

Gutala Ravi

A partition may be made up of two planes of memory cells in a phase change memory. These planes may be configured so that they are not adjacent to one another. In some embodiments, this may mean that the adjacent planes may share sensing circuits, reducing the overall size of the memory array. In addition, by using non-adjacent planes to make up a partition, the planes may be spaced in a way which reduces resistance of power conveying lines. This may mean that smaller sized lines may be used, further reducing the size of the overall array.

Interleaved array architecture

The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

Adaptive wordline programming bias of a phase change memory

Program failures during programming can be corrected during reading using an error correcting code. This allows an array to pass programming more readily, speeding the operation of the memory and avoiding the need to continually reprogram or to issue an error message that the programming was unsuccessful. This makes the memory more user friendly and robust.

Programming bit alterable memories

A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.

Method of storing an indication of whether a memory location in phase change memory needs programming

A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.

Phase-change memory device with error correction capability

A phase change memory may be organized with a global word line coupled to a plurality of blocks, each with a plurality of phase change memory cells arranged in rows and columns. Thus, one global word line may be common to a plurality of blocks. The global word line may be coupled to a word line decoder that is responsible for pulling the word line to ground. Each of the blocks, on the other hand, is coupled to a bitline selector through a bitline. Each block may have its own local word line coupled to the global word line. In some cases, this architecture reduces the minimum capacity of the memory.

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Fairfield, CA, United States of America

Meenatchi Jagasivamani