Juniper Networks, Inc.

Brilliant Telecommunications, Inc.

Brilliant Telecommmunications, Inc.

Meenakshi S Subramanian

Charles Frederick Barry

DeviPrasad Natesan

Tian Shen

Philip Kruzinski

Feng Frank Pan

David R Jorgensen

Reed A Parker

Tian (Alan) Shen

Murthy Garikiparthi

Guochun (George) Zhao

James Michael Murphy

Abhijit Kumar Choudhury

Guochun George Zhao

Keith Eric Holleman

Hank P Nguyen

Feng F Pan

Guochun Zhao

In one example, a network controller manages a network having many network devices. Network devices can receive the timing flow port role assignments from the network controller based on the controller's global view of the network topology. The controller can also calculate timing offsets to be applied to the network devices, based on timestamp information obtained by the network devices via exchanging time synchronization protocol messages, and the controller can update time clocks on all of the network devices within a single window of time, based on a timing offsets calculated in single iteration of calculations.

Controller-based network device timing synchronization

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Apparatus and method of compensating for clock frequency and phase variations by processing packet delay values

In one example, network device includes a control unit having one or more hardware-based microprocessors and an interface. The interface can receive a first time synchronization message from a master device that comprises a first TTL value. The first TTL value can be indicative of a number of hops traversed by the first time synchronization message. The interface can subsequently receive a second time synchronization message from the master device that comprises a second TTL value that is is indicative of a number of hops traversed by the second time synchronization message. The network device can also include a timing module that determines a time adjustment based at least in part on the determination that the first and second TTL values are different, and applies the time adjustment to update the time of the network device.

Time adjustment using time-to-live values

An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

An apparatus comprises a matrix of thermoelectric devices for applying thermal gradients across an electronic component mounted in a PCB substrate within an enclosed housing. A matrix of thermosensitive devices are placed around the perimeter of the electronic component to measure thermal gradients associated with the component. A controller controls the matrix of thermoelectric devices based on the thermal gradients measured by the matrix of thermosensitive devices with a matrix of thermocouple coefficients.

Apparatus and method for thermal stabilization of PCB-mounted electronic components within an enclosed housing

An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.

Apparatus and method of synchronizing distribution of packet services across a distributed network

An apparatus and method are described for forwarding of packets with controlled delay. In one embodiment, the invention includes controlled delay queuing logic to hold a packet in a first class for a queuing time of at least a controlled delay value, and scheduling logic to determine whether to delay transmission of a packet in a second class to allow the transmission of the packet in the first class when the queuing time reaches the controlled delay value.

Apparatus and method of controlled delay packet forwarding

An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.

Growing community of inventors

Santa Clara, CA, United States of America

Meenakshi S Subramanian