Intel Corporation

Meeling Roberts

James P Kardach

Sung-Soo Cho

Waleed S Almulla

Steven M Farrer

Bradley G Heaney

Chandrashekar M Reddy

Gloria Leong

Ronald J Mayer

Scott D Hirose

A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced. When a resume signal is received by the IO subsystem, the slow refresh clock is terminated and the system memory and video memory are again refreshed using a normal faster clock.

Slow memory refresh in a computer with a limited supply of power

An apparatus having a 3.3 volt power supply and a 5 volt power supply, wherein digital signals are processed on a 3.3 volt basis which are translated to a 5 volt basis by a voltage translation circuit before being output. The voltage translator is comprised of an inverter for inverting an input signal. The inverter is powered by the 3.3 volt power supply. A p-channel transistor having its source coupled to the 5 volt power supply and its gate driven by the output of the inverter is implemented. When the inverter generates a low logic, the p-channel transistor is turned on and outputs 5 volts. An n-channel transistor having its source coupled to ground and its gate driven by the output of the inverter is also implemented. When the output of the inverter is 3.3 volts, the n-channel transistor is turned on, which pulls the output to ground. Therefore, when the input signal is at 3.3 volts, a 5 volt signal is output from the voltage translation circuit. When the input signal is at 0 volts, the output signal is, likewise, at 0 volts.

Apparatus for translating logic signal levels from 3.3 volts to 5 volts

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Meeling Roberts