Advanced Micro Devices Corporation

Apple Inc.

Globalfoundries Inc.

Meei-Ling Chiang

Dennis M Fischette, Jr

Emerson S Fang

Sanjeev K Maheshwari

Boon-Aik Ang

Samed Maltabas

Shaobo Liu

Yu Cheng Chen

Alvin Leng Sun Loke

Wei Deng

Dwight K Elvey

Khaled M Alashmouny

Yu Chen

Dabin Zhang

Michael M Oshima

Gregory N Santos

Richard Y Su

Pyoungwon Park

Zhi Hu

Litesh Sajnani

Hairong Yu

The present disclosure describes a circuit having a current source and a load circuit coupled to the current source. The current source can include a transistor electrically coupled to a voltage supply and can be configured to generate a first current with a first current rate-of-change during a time interval, where the first current can be a cancellation current. In addition, the load circuit can be configured to generate a second current with a second current rate-of-change during the same time interval, where the second current can be a load current. The second current rate-of-change can be substantially an inverse of the first current rate-of-change. A power system can include a power management unit configured to generate a power supply voltage at an output, a current source and a load circuit electrically coupled to the output, and a control circuit controls the first current rate-of-change during the time interval.

Power supply noise reduction by current cancellation circuit

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

Reference clock switching in phase-locked loop circuits

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Hybrid asynchronous gray counter with non-gray zone detector for high performance phase-locked loops

A digital PLL is disclosed. In one embodiment, the digital PLL includes a TDC coupled to receive a reference clock signal and feedback signal. The TDC includes a chain of serially-coupled delay elements. An oscillator in the PLL is configured to generate a periodic output signal. A divider is coupled to receive the periodic output signal and generate the feedback signal provided to the TDC. The digital PLL also includes a control circuit. During a phase-locking procedure, each of the serially-coupled delay elements is enabled for fast phase capture. However, once phase-lock has been detected by observing TDC output code, the control circuit is adaptively configured to disable all but a subset of the delay elements for saving power.

Adaptively reconfigurable time-to-digital converter for digital phase-locked loops

A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times.

Phase locked loop system with bandwidth measurement and calibration

A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Automatic amplitude control for voltage controlled oscillator

An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Test techniques for a delay-locked loop receiver interface

A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.

Phase select circuit with reduced hysteresis effect

A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.

Parallel multiplexing duty cycle adjustment circuit with programmable range control

A pipeline ADC (Analog to Digital Converter) unit is provided that has a first and a second multi-stage portion. The first multi-stage portion has a first plurality of converter stages for converting a first analog signal to a first digital signal having a first digital resolution. The second portion has a second plurality of converter stages to convert a second analog signal to a second digital signal having a second digital resolution. The second plurality includes the first plurality. The pipeline ADC unit selectively uses either the first plurality of stages alone, or the second plurality. The pipeline ADC unit may be used in a WLAN (Wireless Local Area Network) communication device.

Variable accuracy pipeline ADC for WLAN communications devices

A digital logic correction (DLC) circuit for a pipeline analog to digital (A/D) converter. The A/D converter having a plurality of stages, each stage producing at least a pair of digital output bits from which a digital representation of an analog input signal can be obtained. The DLC circuit has an adder, the adder having a plurality of inputs and an output. The DLC circuit has a plurality of digital delay sets, each digital delay set comprising at least one digital delay, an input of the digital delay set receiving a corresponding digital output bit and an output of the delay set providing a delayed digital output bit to a respective adder input. The DLC circuit has a clock generator, the clock generator providing clock signals to the DLC circuit to synchronize the arrival of the output of each digital delay set at the adder inputs during a data-valid-period. A primary clock signal is applied to the digital delay sets for every other stage. A secondary clock signal is applied to the remaining digital delay sets. The timing of the primary and secondary clock signals being effective to delay the digital output bits of each stage via the respective digital delay sets to cause the digital output bits to arrive at the adder inputs during the data-valid-period so that the adder produces the digital representation of the analog input signal at the adder output.

Digital logic correction circuit for a pipeline analog to digital (A/D) converter

A pipeline analog to digital (A/D) converter. The pipeline A/D converter having a sample and hold amplifier stage, the sample and hold amplifier stage sampling an analog input signal during a first clock pulse signal. The pipeline A/D converter having an analog signal converter stage, the analog signal converter stage sampling the analog input signal during a first clock pulse signal. According to another aspect of the invention, the pipeline A/D converter converts an analog input signal into a digital representation of the analog input signal. The pipeline A/D converter has a clock generator, the clock generator generating a first clock pulse signal, a second clock pulse signal and a third clock pulse signal. A sample and hold stage samples an analog input signal during the pulse of the first clock signal and holds a sampled voltage signal during the pulse of the second clock signal. A first analog signal converter stage converts and latches the sampled and held voltage signal into a digital output during the pulse of the second clock signal, a most significant bit of the digital representation of the analog input signal being derived from the digital output. The first analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output. The first analog signal converter stage sampling the analog input signal during the pulse of the first clock signal and holding the residue signal during the pulse of the third clock signal.

Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage

A pipeline analog to digital (A/D) converter having a sample and hold stage which samples an analog input signal during a primary clock signal and holds during a secondary clock signal. The A/D converter has an analog signal converter stage which converts and latches the sampled and held voltage signal into a digital output during the secondary clock signal. The analog signal converter stage generating a residue signal based on a comparison of the sampled and held voltage signal and from an analog representation of the digital output, the analog signal converter stage samples the sampled and held voltage signal during the secondary clock signal and holds the residue signal during the primary clock signal. The primary and secondary clock signals together form a two phase nonoverlapping clock having a regular period with a length defined by the duty cycles of the primary and secondary clock signals. The duty cycle of the primary clock signal being less than the duty cycle of the secondary clock signal. According to another aspect of the invention, an A/D converter has a sample and hold stage which samples an analog input signal during a first clock signal and holds a sampled voltage signal during a second clock signal. The A/D converter has an analog signal converter stage, which converts and latches the sampled and held voltage signal into a digital output during the second clock signal. The analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output, the analog signal converter stage samples the analog input signal during the first clock signal and holds the residue signal during a third clock signal. The first clock signal and the second clock signal form a first two phase nonoverlapping clock and the third clock pulse signal forms a second two phase nonoverlapping clock with a fourth clock pulse signal. The fourth clock signal having a duty cycle of less than, greater than or equal to 50% of the period of the second nonoverlapping clock, and the pulse of the first clock signal and the pulse of the second clock signal both overlapping with the pulse of the fourth clock signal. The duty cycle of the first clock signal is optionally less than the duty cycle of the second clock signal.

Pipeline analog to digital (a/d) converter with lengthened hold operation of a first stage

A pipeline analog to digital (A/D) converter for converting an analog input signal into a digital representation of the analog signal. The pipeline A/D converter has a sample and hold stage, the sample and hold stage sampling and holding the analog input signal and outputting a sampled and held signal. The pipeline A/D converter also has a first analog signal converter stage, the first analog converter stage producing a digital output based on the sampled and held signal, from which a most significant bit of the digital representation of the analog input signal is derived. The first analog converter stage produces a residue signal based on a comparison of the analog input signal and an analog representation of the digital output. The pipeline A/D converter has at least one additional stage, the additional stage producing a subsequent digital output based on the residue signal produced by the first analog signal converter stage, at least one bit which is less significant than the most significant bit being derived from the subsequent digital output.

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Cupertino, CA, United States of America

Meei-Ling Chiang