University of Alabama

Sandisk Technologies Inc.

Md Raquibuzzaman

Biswajit Ray

Ravi J Kumar

Sujjatul Islam

Aleksandar Milenkovic

Preeti Kumari

Umeshwarnath Surendranathan

Matchima Buddhanoy

A system for performing sanitization of multi-level cell (MLC) memory has a memory controller configured to read and buffer at least a first page of MLC memory that shares MLCs with at least a second page. The memory controller sanitizes the second page by performing at least one write operation to adjust the charge levels in the MLCs so that each bit of the second page is forced to the same value or to a value that mirrors the value of another bit of the same cell. Thus, for multiple pages sharing the same MLCs, the data of at least one page can be sanitized while the data of at least one other page is retained. Such sanitizing can be achieved without having to perform an erase operation, thereby helping to prevent or reduce memory degradation.

Systems and methods for sanitization of multi-level cell (MLC) memory

An apparatus includes a control circuit configured connect to non-volatile memory cells. The control circuit is configured to receive a read command directed to data stored in non-volatile memory cells of a first word line and determine that a second word line adjacent to the first word line is sanitized. The control circuit is further configured to select an adjusted read voltage for a read operation directed to the non-volatile memory cells of the first word line based on the determination.

Read schemes with adjustment for neighboring word line sanitization

A system for testing memory includes logic that is configured to perform various normal memory operations (e.g., erase, read and write operations) on a memory device and to determine operational parameters associated with the memory operations. As an example, the amount of time to perform one or more memory operations may be measured, a number of errors resulting from the memory operations may be determined, or a number of memory cells storing noisy bits may be identified. One or more of the operational parameters may then be analyzed to determine whether they are in a range expected for counterfeit or defective memory. If so, the logic determines that the memory under test is counterfeit or defective and provides a notification about such determination.

Systems and methods for detecting counterfeit or defective memory

Growing community of inventors

Huntsville, AL, United States of America

Md Raquibuzzaman