Texas Instruments Corporation

Md Abidur Rahman

Sualp Aras

Brett E Smith

Adam Quirk

Ankur Chauhan

Subrato Roy

Eung Jung Kim

Kyle Clifton Schulmeyer

Vikrant Dhamdhere

Stephen Nortman

David John Baldwin

Sudheer Prasad

Xiaochun Zhao

Huijuan Li

Tri Cao Nguyen

Zheng Li

William E Grose

Wenchao Qu

Vijay Krishnamurthy

Min Chu

Vinayak Hegde

Tikno Harjono

Kuntal Joardar

Gary Eugene Daum

Tianhong Yang

Guhaprakash Amudhan

Sathish Vallamkonda

Hector X Roman

Cameron Wayne Phillips

A load switch includes a switch input, a switch output, a first field-effect transistor (FET), and a second FET. The switch input is adapted to be coupled to a controller output of a controller. The switch output is adapted to be coupled to a controller input of the controller. The first FET has a gate and a source. The gate of the first FET is coupled to the switch input. The second FET has a gate and a source. The gate of the second FET is coupled to the source of the first FET. The source of the second FET is coupled to the switch output.

Fault voltage scaling on load switch current sense

A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Clamp for power transistor device

A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.

Method of achieving robustness of the device in short circuit condition by adjusting the current limit threshold based repetitive fault condition

State machine controlling power transistor through fault and no fault

An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

Power transistors with a resistor coupled to a sense transistor

A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.

Safe operating area energy limit system and method in power application

A circuit protective system. The system has: (i) an input for sensing an operational voltage responsive to a current flowing through a transistor; (ii) circuitry for applying a forced voltage at the input; (iii) voltage-to-current conversion circuitry for outputting a reference current in response to the forced voltage at the input; (iv) circuitry for providing a reference trim current in response to a trim indicator; and (v) comparison circuitry for outputting a limit signal in response to a comparison of the reference current and the reference trim current.

High current limit trim apparatus and methodology

Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

Methods and apparatus for compensation and current spreading correction in shared drain multi-channel load switch

An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Current sensing and control for a transistor power switch

A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.

Circuit reliability improvement by detecting and mitigating high voltage transient event at supply

Protective circuit enabling different bias levels responsive to event faults

An output discharge circuit for a load switch may include a capacitor coupled between a power rail of the output discharge circuit and a ground lead, and a diode coupled between a power input of the output discharge circuit and the power rail. The output discharge circuit may charge the capacitor via a current path formed by the diode while power is being supplied to the load switch. When the power supply to the output discharge circuit is turned off, the diode may prevent the capacitor from discharging through the current path, and the stored charge on the capacitor may be used to power the output discharge switch for a period of time after the power supply has been turned off. In this way, the output discharge circuit may continue to discharge the output of the load switch even when power is no longer being supplied to the load switch.

Output discharge techniques for load switches

This disclosure describes techniques for generating relatively low regulated power supply voltages over a relatively wide range of input voltages. The techniques for generating the regulated voltages may include using at least two different pass transistors to regulate an output voltage of a voltage regulator. Both the turn-on threshold voltage and the maximum drain-to-source voltage rating of the first pass transistor may be greater than the corresponding characteristics of the second pass transistor. Using two different pass transistors with two different turn-on threshold voltages and two different maximum drain-to-source voltage ratings may increase the range of voltages over which a voltage regulator can generate a relatively low output voltage relative to the range of voltages that would be allowable if a single type of pass transistor were used.

Wide input range, low output voltage power supply

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.

Growing community of inventors

Richardson, TX, United States of America

Md Abidur Rahman