At&t Bell Laboratories

McDonald Robinson

George K Celler

David J Lischner

Adrian R Hartman

Harry T Weston

Gee-Kung Chang

Yiu H Wong

High-speed p-i-n and avalanche photodetectors (photodiodes) use a heavily doped buried layer to greatly limit minority carriers generated by incident light in the buried layers and the substrates of the devices from reaching the cathodes and thus enhances response time while substantially decreasing dark current. A p-i-n diode of this type with a 1.1 square millimeter active area can operate with 4 volt reverse bias and is capable of having edge rise and fall times in the 4 nanosecond range.

P-I-N and avalanche photodiodes

A semiconductor structure including a pair of single-crystal semiconductor bulk regions (10.3, 12.2) of differing first and second bulk conductivities, respectively, for forming semiconductor circuits therein, is fabricated whereby each such region is electrically isolated from the other and from a rigid body (20) supporting these regions. The structure is formed by forming at a major surface of a single crystal semiconductor water (10) having the first bulk conductivity a bulk zone (12.1) having the second bulk conductivity, followed by the steps of (1) forming in the wafer (10) at the major surface (10.6) thereof a V-shaped groove (10.2) at the boundary of the bulk zone (12.1) using a crystallographic orientation dependent etch, in order to define the regions (10.3, 12.2) of differing conductivities, (2) forming a dielectric layer (15.1, 15.2) upon the walls of the V-groove and upon the exposed portion of the major surface, (3) forming a rigid body layer (20), such as polysilicon, upon the dielectric layer (15.1, 15.2), and (4) planarizing the exposed, opposed major surface of the single crystal medium down to the vertices of the V-grooves. The semiconductor circuits themselves can then be fabricated in the resulting mutually dielectrically isolated regions (10.3, 12.2).

Isolation process for high-voltage semiconductor devices

Dielectrically isolated semiconductor devices are producible through a relatively convenient fabrication procedure. In this fabrication procedure, a substrate having regions of single crystal silicon and regions of silicon oxide is employed. Such substrate is expeditiously produced by methods which leave the surface of the single crystal regions below those of the silicon oxide regions. Silicon is deposited by CVD onto the structure with its regions of silicon dioxide and single crystal silicon. Initially, the conditions of the CVD procedure are controlled so that epitaxial silicon grows on the regions of single crystal silicon but essentially no growth is induced on the silicon oxide regions. When the growth of the single crystal regions has proceeded sufficiently to produce a substantially planar structure, advantageously the deposition conditions are adjusted so that silicon is also deposited on the surface of the silicon oxide. The polycrystalline or amorphous silicon layer overlying regions of silicon oxide produced from this growth is then converted into single crystal silicon.

Process for producing dielectrically isolated silicon devices

Structures useful for dielectrically isolated high voltage devices are produced utilizing a melting technique. In this technique a cavity is produced in a silicon wafer, the surface of the cavity is, for example, oxidized to form a dielectric material, and silicon is deposited onto the dielectric material so that it extends to a region where it is in contact with single crystal silicon, e.g., a portion of the wafer. The entire region of polycrystalline silicon is then melted. Upon termination of the melting energy, the polycrystalline silicon is converted into a thick region of dielectrically isolated single crystal silicon. This thick region is useful for the formation of high voltage devices.

Method of making dielectrically isolated silicon devices

Dielectrically isolated regions of single crystal silicon are produced through the use of a specific melting process. In this process, a substrate having regions of single crystal silicon contacting regions of non-single crystal silicon that overlie a dielectric material are treated. In particular, the entire region(s) of non-single crystal silicon is melted utilizing primarily radiant energy. Cooling is then initiated and the molten silicon is converted into a region of single crystal material. Isolation is completed by removing the appropriate regions of single crystal silicon.

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Chester, NJ, United States of America

McDonald Robinson