Intel Corporation

Intel Corporatio

Mazen G Gedeon

Barnes Cooper

Robert E Gough

Basavaraj B Astekar

Michael Berger

Eli Elik Kupermann

Sean Dardis

Mukesh Kataria

Joshua Resch

Michael N Derr

Yasser Rasheed

David Birnbaum

Zhenyu Zhu

Soethiha Soe

Jeffrey Tripp

Hung Huynh

Jeffrey John Vick

Aditya Bhutada

Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI primary device to an eSPI secondary device. In embodiments, the eSPI primary device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI primary device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI primary device and the eSPI secondary device. Other embodiments may be described and/or claimed.

Enhanced serial peripheral interface (eSPI) signaling for crash event notification

An electronic device may be provided that includes a first controller, a second controller, and a bus to connect between the first controller and the second controller. The electronic device may also include a first signal line between the first controller and the second controller, and the first controller to provide a first signal on the first signal line to the second controller to wake up the second controller from a low power mode.

Electronic device having a controller to enter a low power mode

A platform including a security system is described. The security system comprises, in one embodiment, a multi-state system having a plurality of modes, available whenever the platform has a source of power. The modes comprise an unarmed mode, in which the security system is not protecting the platform, an armed mode, in which the platform is protected, the armed mode reached from the unarmed mode, after an arming command, and a suspecting mode, in which the platform is suspecting theft, the suspecting mode reached from the armed mode, when a risk behavior is detected.

Always-available embedded theft reaction subsystem

Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.

System and method for causing reduced power consumption associated with thermal remediation

Various embodiments are directed to a tri-layered power scheme for architectures which contain a microcontroller. In one embodiment, a power management system may comprise a microcontroller in a chipset, a low consumption power well to control a power supply to the microcontroller, and a power controller to control a power supply to the low consumption power well. The power management system may be arranged to switch among multiple power consumption states. In a maximum power consumption state, the microcontroller is on, the power controller is on, and the low consumption power well is on. In an intermediate power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is required to be on. In a minimum power consumption state, the microcontroller is off, the power controller is on, and the low consumption power well is optionally on or off at the discretion of the power controller. Other embodiments are described and claimed.

Tri-layered power scheme for architectures which contain a micro-controller

An apparatus and method for measuring and controlling power consumption of a computer system utilizing sensing circuitry. The sensing circuitry simultaneously senses the power consumption for each one of various components in the computer system, including the Central Processing Unit (CPU). The power consumption data is accumulated and sent to CPU in order to enable the CPU to control power of the various components of the computer system, including the CPU itself.

Apparatus and method for measuring and controlling power consumption of a computer system

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Beaverton, OR, United States of America

Mazen G Gedeon