Applied Materials, Inc.

Mayur G Kulkarni

Sanjeev Baluja

Kalyanjit Ghosh

Praket Prakash Jha

Deenesh Padhi

Kien Nai Chuc

Hang Yu

Yanjie Wang

Sungjin Kim

Leon Volfovski

Madhu Santosh Kumar Mutyala

Akshay Dhanakshirur

Saketh Pemmasani

Bok Hoen Kim

Xinhai Han

Krishna Nittala

Michael Wenyoung Tsiang

Hyung Jin Park

Sang Hyuk Kim

Ryeun Kwan Kim

Jason K Foster

Majid K Shahreza

Myung Hun Ju

Jin Chul Son

Saiprasanna Gnanavelu

Michael Robert Rice

Juan Carlos Rocha-Alvarez

Ganesh Balasubramanian

Jian Li

Amit Kumar Bansal

Kwangduk Douglas Lee

Paul Brillhart

Ren-Guan Duan

Ajit Balakrishna

Dmitry A Dzilno

Tejas Ulavi

Zhijun Jiang

Dale R Dubois

Sanjay G Kamath

Daemian Raj Benjamin Raj

Shailendra Srivastava

Kaushik Comandoor Alayavalli

Xiaopu Li

Alex Minkovich

Yuxing Zhang

Shawyon Jafari

Yusheng Zhou

Wei Min Chan

Priyanka Dash

Zongbin Wang

Akshay Gunaji

Jun Tae Choi

Qiang Ma

Daniel Hwung

Lei Guo

Udit S Kotagi

Sandeep Bindgi

Yong Xiang Lim

Yubin Zhang

Junghoon Sun

Arun Thottappayil

Gregory Siu

Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support disposed within the chamber body. The substrate support may define a substrate support surface. The chambers may include a showerhead positioned supported atop the chamber body. The substrate support and a bottom surface of the showerhead may at least partially define a processing region within the semiconductor processing chamber. The showerhead may define a plurality of apertures through the showerhead. The bottom surface of the showerhead may define an annular groove or ridge that is positioned directly above at least a portion of the substrate support.

Shaped showerhead for edge plasma modulation

Exemplary methods of semiconductor processing may include delivering a deposition precursor into a processing region of a semiconductor processing chamber. The methods may include depositing a layer of material on a substrate housed in the processing region of the semiconductor processing chamber. The processing region may be maintained at a first pressure during the deposition. The methods may include extending a baffle within the processing region. The baffle may modify a flow path within the processing region. The methods may include forming a plasma of a treatment or etch precursor within the processing region of the semiconductor processing chamber. The processing region may be maintained at a second pressure during the forming. The methods may include treating the layer of material deposited on the substrate with plasma effluents of the treatment precursor. The processes may be cycled any number of times.

Dynamic processing chamber baffle

Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.

Multi-pressure bipolar electrostatic chucking

Exemplary semiconductor processing chambers may include a gasbox. The chambers may include a substrate support. The chambers may include a blocker plate positioned between the gasbox and the substrate support. The blocker plate may define a plurality of apertures through the plate. The chambers may include a faceplate positioned between the blocker plate and the substrate support. The faceplate may be characterized by a first surface facing the blocker plate and a second surface opposite the first surface. The faceplate may be characterized by a central axis. The faceplate may define a plurality of apertures through the faceplate distributed in a number of rings. Each ring of apertures may include a scaled increase in aperture number from a ring radially inward. A radially outermost ring of apertures may be characterized by a number of apertures reduced from the scaled increase in aperture number.

Faceplate with localized flow control

Exemplary substrate support assemblies may include an electrostatic chuck body that defines a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. A density of the plurality of protrusions within an outer region of the substrate support surface may be greater than in an inner region of the substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include an electrode embedded within the electrostatic chuck body.

Low impedance current path for edge non-uniformity tuning

Exemplary substrate support assemblies may include a chuck body defining a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. The substrate support surface may define an annular groove and/or ridge. A subset of the plurality of protrusions may be disposed within the annular groove and/or ridge. The substrate support assemblies may include a support stem coupled with the chuck body.

Mesa height modulation for thickness correction

A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

Process kit for a high throughput processing chamber

Implementations disclosed herein generally provide a lift pin that can improve the deposition rate and uniform film thickness above lift pin areas. In one implementation, the lift pin includes a first end coupling to a shaft, the first end having a pin head, and the pin head having a top surface, wherein the top surface is planar and flat, and a second end coupling to the shaft, the second end having a flared portion, wherein the flared portion has an outer surface extended along a direction that is at an angle of about 110&#xb0; to about 140&#xb0; with respect to a longitudinal axis of the lift pin.

Enhanced lift pin design to eliminate local thickness non-uniformity in teos oxide films

Embodiments disclosed herein generally relate to systems and methods to prevent free radical damage to sensitive components in a process chamber and optimizing flow profiles. The processing chamber utilizes a cover substrate on lift pins and an inert bottom purge flow to shield the substrate support from halogen reactants. During a clean process, the cover substrate and the purge flow restricts halogen reactants from contacting the substrate support. The method of cleaning includes placing a cover substrate on a plurality of lift pins that extend through a substrate support in a processing chamber, raising the cover substrate via the lift pins to expose a space between the cover substrate and the substrate support, supplying a halogen containing gas into the processing chamber, supplying a second gas through an opening in the processing chamber, and flowing the second gas through the space between the cover substrate and the substrate support.

Method and system for high temperature clean

Systems and methods for depositing a film in a PECVD chamber while reducing residue buildup in the chamber. In some embodiments disclosed herein, a processing chamber includes a chamber body, a substrate support, a showerhead, and one or more heaters configured to heat the showerhead. In some embodiments, the processing chamber includes a controller.

System and method for substrate processing chambers

Embodiments of the present disclosure generally relate to an improved method for forming a dielectric film stack used for inter-level dielectric (ILD) layers in a 3D NAND structure. In one embodiment, the method comprises providing a substrate having a gate stack deposited thereon, forming on exposed surfaces of the gate stack a first oxide layer using a first RF power and a first process gas comprising a TEOS gas and a first oxygen-containing gas, and forming over the first oxide layer a second oxide layer using a second RF power and a second process gas comprising a silane gas and a second oxygen-containing gas.

VNAND tensile thick TEOS oxide

Apparatus and methods for depositing a film in a PECVD chamber while simultaneously flowing a purge gas from beneath a substrate support are provided herein. In embodiments disclosed herein, a combined gas exhaust volume circumferentially disposed about the substrate support, below a first volume and above a second volume, draws processing gases from the first volume down over an edge of a first surface of the substrate support and simultaneously draws purge gases from the second volume upward over an edge of a second surface of the substrate support. The gases are than evacuated from the combined exhaust volume through an exhaust port fluidly coupled to a vacuum source.

Application of bottom purge to increase clean efficiency

Embodiments of substrate supports with a heater are provided herein. In some embodiments, a substrate support may include a first member to distribute heat to a substrate when present above a first surface of the first member; a heater coupled to the first member and having one or more heating zones to provide heat to the first member; a second member disposed beneath the first member; a tubular body disposed between the first and second members, wherein the tubular body forms a gap between the first and second members; and a plurality of substrate support pins disposed a first distance above the first surface of the first member, the plurality of substrate support pins to support a backside surface of a substrate when present on the substrate support.

Substrate support with heater

Growing community of inventors

Bengaluru, India

Mayur G Kulkarni