Synopsys, Inc.

Mayukh Bhattacharya

Shan Yuan

Chih Ping Antony Fan

Michael Durr

Chih-Ping Antony Fan

Michal Jerzy Rewienski

Huiping Huang

Peilin Jiang

Antony Fan

Amelia Huimin Shen

Kiran Kumar Gullapalli

Jonti Talukdar

Pallab Dasgupta

Kevin J Kerns

Amit Patra

Aleksandrs Krjukovs

Beatrice Solignac

Mira Tzakova

Rayson Yam

Vinay Nulkar

Svetlana Rudnaya

Mihir Sherlekar

Miroslava Tzakova

Sayandeep Sanyal

A system and method for inserting test points during circuit design testing are presented. The method includes partitioning a circuit design into a plurality of blocks and determining a first potential defect and a second potential defect for the circuit design. The method also includes simulating the circuit design by injecting, into the circuit design, the first potential defect to produce a first set of outputs of the plurality of blocks and simulating the circuit design by injecting, into the circuit design, the second potential defect to produce a second set of outputs of the plurality of blocks. The method further includes determining a set of output nodes of the plurality of blocks and generating a test that, when executed, measures signals at the set of output nodes.

Test point insertion in analog circuit design testing

A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

Measuring device defect sensitization in transistor-level circuits

This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.

Finding equivalent classes of hard defects in stacked MOSFET arrays

A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.

Method and system for custom model definition of analog defects in an integrated circuit

In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors. A transistor-level circuit simulation of the circuit's response to an input stimulus is performed, based on the transistor-level description of the circuit. Activity levels for the transistors in the circuit are determined from the transistor-level circuit simulation. A graphical representation of the circuit is rendered. The graphical representation contains graphical elements that represent components of the circuit, and the graphical elements are visually coded according to the activity levels of the transistors in the corresponding components.

Visual representation to assess quality of input stimulus in transistor-level circuits

Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.

Automatic test pattern generation (ATPG) for parametric faults

A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.

Transistor&#x2014;level defect coverage and defect simulation

A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

Fast and scalable methodology for analog defect detectability analysis

A method, apparatus, and/or computer program product can perform an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.

Defect weight formulas for analog defect simulation

A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios. Further, the method comprises generating, with a processor and for the first sampling size, a confidence score for each of the plurality of bins based on the error value for each of the plurality of coverage scenarios, and outputting the confidence score for each of the plurality of bins.

Guiding sample size choice in analog defect or fault simulation

A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.

Visual representation of circuit related data

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances Cand C, and at least one of capacitances Cand Cexceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances Cand Chas a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances Cand Chave high capacitances, then lump capacitances can be used at the two nets for the simulation.

Method of optimizing capacitive couplings in high-capacitance nets in simulation of post-layout circuits

A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

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Palo Alto, CA, United States of America

Mayukh Bhattacharya