Cisco Technology, Inc.

Stmicroelectronics Gmbh

Hewlett-packard Company

Scientific-atlanta, Inc.

Other

Maynard Darvel Hammond

Charaf Hanna

Zhifang J Ni

Benjamin Nelson Darby

Gale L Shallow

Andrew Graham Whitlow

Kinney Chapman Bacon

Michael R Diehl

Anthony John Wasilewski

Glendon Leo Akins, Iii

Gary L Logston

Jonathan Bradford Evans

David L McAllister

Douglas F Woodhead

James M Dewey

John Wrobbel

Paul Rimas Zalkauskas

Richard A Powers

Francis Cheung

A method is provided in one example and includes receiving a plurality of packets; identifying whether a particular packet, of the plurality of packets, is part of a sequenced flow; identifying whether a particular sequence number of the particular packet is being received within a time window; identifying whether the particular packet was a next expected packet for a particular flow; and forwarding the particular packet to a next destination. In more particular embodiments, packet inspection is used to set one or more flags for identifying characteristics associated with the plurality of packets. Certain packets in non-sequenced flows are routed directly from an input interface to an output interface of a resequencer module using a flow-through packet path.

Apparatus, system, and method for resequencing packets

A system and method for improved upstream data transmission. In an embodiment, a cable modem includes a transceiver configured for transmitting data upstream once permission is granted. In between times when permission to transmit is granted, however, the cable modem is configured to prepare as much data as possible for immediate upstream transmission once that very permission is granted. Thus, prior to permission being granted, the cable modem assembles (pre-processes) the data into transmit frames such that the data frames may be stored in a local memory coupled to the transceiver in a 'ready-to-go' format. In this manner, the entire amount of time/bandwidth allocated to the cable modem in response to its request for upstream data transmission may be dedicated to actually transmitting data upstream as opposed to consuming time and bandwidth processing the data into data frames after upstream data transmission has been granted.

System and method for improved upstream transmission

A filter in a DOCSIS bridge performs IP Filtering of incoming Ethernet packets in hardware. The filter includes a parser circuit which, in hardware, parses each of the incoming Ethernet packets and then utilizes the parsed information in combination with a content-addressable memory (CAM) that stores filtering information, to filter and route the incoming Ethernet packets. Detailed statistical data may also be generated to provide information on the type of filtering being performed by the DOCSIS bridge.

Hardware implemented ethernet multiple tuple filter system and method

A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an 'acknowledgement' that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.

System and method for efficient upstream transmission using suppression

In a subscriber television system with a host terminal, the present invention allows the identification of the individual packets from two separate MPEG transport streams that have been multiplexed together for decoding by a single external conditional access or point-of-deployment (POD) module. The decoding of individual packets from two separate MPEG transport streams supports the use of multiple tuner host terminals for such functions as picture-in-picture (PIP) program viewing and the viewing of one program while recording a second program.

Method of identifying multiple digital streams within a multiplexed signal

A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations

A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor. Finally, the system includes a controller, responsive to the enable bit, configured to transfer data directly from the data transfer queue to the ancillary processor, the controller being operative to evaluate the at least one data ready bit and transfer the associated block of data from the queue to the ancillary processor if the at least one data ready bit indicates that the data is ready for transfer.

Method and apparatus for performing high speed data transfers between a

The present invention provides a method and apparatus for receiving and synchronizing data transmitted to a host interface unit of a graphics memory system on the rising and falling edges of a strobe signal in accordance with an accelerated graphics port (AGP) specification. An inner loop synchronization component, which is comprised in the host interface unit of the graphics memory system, receives data transmitted to the host interface unit on the falling and rising edges of a strobe signal and synchronizes the data to a PCI clock signal. The inner loop synchronization component comprises a first data transfer unit, a second data transfer unit and a control unit. The first data transfer unit comprises logic configured to capture the data transmitted on the falling edge of the strobe signal and to delay the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the first data transfer unit. The control unit detects the falling edge of the strobe signal and generates one or more timing signals based on the strobe signal. The rising edge of the strobe signal may or may not occur within the PCI clock cycle in which the falling edge of the strobe signal occurs. The second data transfer unit receives the timing signals generated by the control unit and utilizes the timing signals to capture the data transmitted on the rising edge of the strobe signal. The second data transfer unit then delays the captured data a predetermined number of cycles of the PCI clock before outputting the captured data from the second data transfer unit. The timing signals generated by the control unit are utilized by the second data transfer unit to ensure that the data transmitted on the rising edge of the strobe signal is output from the second data transfer unit in the same cycle of the PCI clock in which the data transmitted on the falling edge of the strobe signal is output from the first transfer unit.

Method and apparatus for synchronizing data received in an accelerated

In a system that transmits packets containing timestamps and information from a transmission site to a reception site at a transmission bit rate the packets may experience jitter, i.e. variable delay, during transmission. In such a case, the packets are temporally shifted relative to the timestamps and to other packets. Where the timestamp values are inserted into selected packets prior to transmission and that timestamp represent the value of the transmission site clock, the method and apparatus of the present invention substantially removes the jitter and adjusts the timestamp values prior to reception of the packets at the reception site. The present invention achieves this goal by receiving the packets at an intermediate site that has a local clock operates at a nominal frequency substantially equal to the nominal frequency of the transmission site clock and uses that clock as a jitter-free clock to correct the packets. The packets are stored in a buffer at the intermediate site and output from the buffer at a controlled rate to maintain a substantially constant average transit time of packets through the buffer. Before the packets are output for reception at the reception site the timestamps of selected packets are modified to reflect the new temporal relationship between packets due to the controlled rate of output from the intermediate site.

Method and apparatus for removing jitter and correcting timestamps in a

Packets of data, some of which may carry a timestamp value, are transmitted through an Asynchronous Transfer Mode (ATM) network. Prior to transmission, each packet of data is encapsulated in a respective convergence sublayer protocol data unit (CS-PDU) having a header portion and a payload portion. The header portion of each CS-PDU contains a time correction indicator (TCI), which indicates whether the CS-PDU carries a packet of data having a timestamp value that may require correction after the CS-PDU passes through the network, and a time reference correction (TRC) field. Each CS-PDU is then segmented into a plurality of successive segments; a first one of the segments of each CS-PDU contains the CS-PDU header. Each segment is then inserted into the payload section of a respective ATM cell for transmission through the network. At each node in the network, cells are examined to determine if they contain a CS-PDU header. If a cell contains a CS-PDU header, any variable delays imposed upon that cell as it passed through the node are measured and added to the TRC field in the CS-PDU header prior to sending the cell to the next node. At a destination node, the accumulated TRC value may be added to the time stamp value of the packet carried in the CS-PDU in order to compensate for the variable delays imposed upon that packet as the cells carrying the packet traversed the network.

Growing community of inventors

Lawrenceville, GA, United States of America

Maynard Darvel Hammond